EDA360, verification, UVM, and the future of EDA standards

Adam Sherilog Sherer, the Cadence Incisive Product Management Director, just published a blog about his experience in calling on several existing customers to discuss UVM (The Universal Verification Methodology being developed under Accelera’s banner). (“We Want UVM 1.0! When Do We Want it? Now!“)

I found the mix of what these customers are currently using to be very interesting:

  • OVM SystemVerilog users and one Vera–>OVM migration
  • VMM users
  • Custom SystemVerilog library users

That’s a pretty diverse cross section of verification methodologies and Sherilog found they are all preparing to migrate to UVM by next year based on what they now know about support plans. There are many companies working to make UVM successful, as Sherilog points out in his blog and this seems to me to be a pretty good example of a place where standards can really help the industry.

One of the underlying ideas of EDA360 is that no one EDA company can do it all and that, for the good of the industry, we need all kinds of standards to work with. UVM is just one example and a big chunk of the verification vendors are lining up behind it. Expect more of this sort of collaboration in the future across the Realization spectrum (System, SoC, and Silicon).

Be sure to read the blog: “We Want UVM 1.0! When Do We Want it? Now!

About sleibson2

EDA360 Evangelist and Marketing Director at Cadence Design Systems (blog at https://eda360insider.wordpress.com/)
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