What’s Broken in EDA: Qualcomm’s Radojcic, Mindspeed’s Dahaliwal, GlobalFoundries’ Brotman, and EDA gadabout McLellan

Earlier this month, the System Level Design Community published an interview where Ed Sperling interviews Riko Radojcic, director of engineering for CDMA Technologies at Qualcomm; Surinder Dahaliwal, executive director for VLSI Core Engineering at Mindspeed Technologies; Andy Brotman, vice president of design infrastructure at GlobalFoundries, and Paul McLellan, a start-up CEO and blogger. He asks them the question: “What’s broken in EDA?” The answers are illuminating and they are in complete agreement with and reinforce the EDA360 vision. Here are some salient statements from the interviews:

Radojcic: “Twenty years ago a young engineer could understand everything from beginning to end. Now, there are at least five different languages and cultures. Process guys have become material scientists. System designers have a different language. Interdisciplinary communication is very hard. That’s all the more reason why you need a structured layer to bridge that and allow co-design.”

Brotman: “I’m not sure it’s a matter of people not communicating. It’s that they don’t understand the other team’s task and how it will interact with what they’re building. If we could combine that in one place then we would solve it everywhere.”

Dahaliwal: “The key handoff points between architecture, system and implementation—that layer is missing.”

McLellan: “The attraction is the block-level of the chip. The design folks don’t acknowledge that what we’re doing today is integration, not assembling RTL all the way down to the gates. It’s mostly IP assembly. That’s also the level the software guys need to put together their platform. That level is an interesting opportunity for standardization and to be able to go up from that level or down from that level.”

You can read the entire discussion here.


About sleibson2

EDA360 Evangelist and Marketing Director at Cadence Design Systems (blog at https://eda360insider.wordpress.com/)
This entry was posted in EDA360, Silicon Realization, SoC Realization, System Realization. Bookmark the permalink.

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