Yesterday, Cadence introduced a holistic approach to IC design that the company calls Silicon Realization. (Get the White Paper here.) I’m already fielding questions from my friends about what “holistic” means in this context and what’s new about all this. When Cadence uses the term “holistic,” it means an entire tool chain that revolves around three critical requirements: unified design intent, abstraction, and convergence. “Design intent” includes representations of functional, physical, and electrical characteristics with the requirement that these representations be consistent throughout the implementation and verification tool sets; that they span the various abstraction levels used to represent the design; and that all members of the IC design team can easily make use of the representations at all design levels.
Central to this idea is one database that can accommodate all of the required representations. It should not be a surprise to learn that the OpenAccess is the database that Cadence has in mind for this task. One example of unified design intent representation is the CPF (Common Power Format), which is an Si2 industry standard. Other examples of such representations are common constraint definitions that span the analog and digital design domains and verification metrics. Without a doubt, these representations need standard formats like CPF to succeed and Cadence strongly supports the development of such standards.
Every member of an IC design team understands abstraction. Abstraction is a part of life in the complex world of IC design and it always has been. We’ve been moving up the EDA abstraction curve since the 1970s. Polygons and transistors (back when EDA was called “IC CAD”) were abstracted into gates during the 1980s. Gates were then abstracted into RTL during the 1990s. We still have gates, transistors, and polygons, but we also have tools to handle them automatically. Abstraction allows designers to save time and it allows design tools to gain execution speed by making simplified representations and models of complex blocks. Two examples of abstraction already in use by IC designers include Verliog-AMS wreal models and TLM (transaction-level modeling) for system-level development using SystemC. Here again, a database with access to all model forms for a block allows different designers using different tools to manipulate a design in a consistent manner that does not require the design to exist in multiple forms, which can prevent problems caused by concurrent work done on inconsistent versions of a design.
Finally, there’s convergence—the ability of a tool set to make consistent forward progress on a design with respect to function, power, performance, cost, and packaging goals. A convergent tool set allows the design team to make incremental design changes and refinements while continuing to head towards project completion in a steady, direct manner. Convergence’s goal is to allow rapid design closure with a minimum number of design iterations while accommodating those inevitable ECOs (engineering change orders) with minimal disruption to the project. These goals are completely noncontroversial.
So what is so controversial about Silicon Realization?
This: Cadence believes that the fastest path to a holistic Silicon Realization approach is an end-to-end flow, which Cadence is basing on the Encounter Digital Implementation System, the Virtuoso custom layout suite, the Incisive verification suite, and the Allegro packaging and printed-circuit board tool set. These tools are all closely interconnected by the OpenAccess database so that they can communicate and use design intent; they can handle design abstraction; and they can support a convergent design process.
“Nontraditional!” is a common reaction to this holistic perspective. After all, the EDA industry has spent the last 20 years developing a point-tool approach where every design team must assemble and integrate a huge stack of tools to get an end-to-end tool flow. As IC process technology has evolved, the number of design tools needed to reach tapeout has steadily climbed to the point where the tool-selection and tool-integration process is no longer clear cut or simple. In fact, getting the tools to simply work together is a major task in itself.
“Nontraditional!” comes the cry once again.
Actually, it’s not. If you go all the way back to the earliest days of the ASIC revolution, to the days of gate arrays, it was traditional for the gate-array supplier to supply all of the tools—because the tools were closely wedded to the gate-array design and associated process technology. That’s just the way it was done. It was…traditional.
So just what is “traditional,” and why?
If you think this holistic approach to Silicon Realization is something that merely serves the corporate interest, consider this paragraph from Paul McLellan’s book EDA Graffiti:
“In the current hyper-cost-sensitive environment I think that the pendulum will swing back the other way towards these more integrated flows and away from the integrate-your-own-point-tools approach. It is also the only way that complex factors like power—that cut across the whole design flow—can be accommodated.”
McLellan has spent more than 25 years in the EDA industry. In fact, he started at VLSI Technology in the gate-array days. He’s seen the pendulum swing from the original integrated EDA flow to what we have today and he’s clearly calling for a swing in the opposite direction to manage the complexity that now threatens to overwhelm IC design.
Few people have McLellan’s “holistic” perspective of the ASIC and SoC world. It’s a perspective bred of experience. If you’d like to get more insight into McLellan’s EDA and IC-design views, order his book, EDA Graffitti, here. It’s probably the least expensive EDA tool you’ll ever buy.