Scary story of FPGA verification for Halloween

Triggered by one of my posts (“Will verification challenges overwhelm FPGA design?”) and one by GateRocket’s Dave Orecchio, UVM/OVM Product Marketing Group Director Tom Anderson has just recounted one of his experiences with FPGA verification at a company that may have been done in by its inability to troubleshoot a complex FPGA design. His blog entry, titled “The Increasingly Hazardous World of FPGA Verification” is worth a read before you head out into the weekend world of zombies, vampires, and goblins.

Trick or treat!


About sleibson2

EDA360 Evangelist and Marketing Director at Cadence Design Systems (blog at
This entry was posted in EDA360, SoC Realization, System Realization. Bookmark the permalink.

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