Intel says Moore’s Law alive and well and living at 32nm

One of the really interesting presentations at least week’s 8th International SoC Conference in Irvine was from Dr Jeff Parkhurst, Research Programs Manager at Intel, who spoke on the topic of “Delivering Cost-effective SoC-Based Platform Solutions.” I found the presentation eye-opening because of the insights it gave me into the current state of the art in chip manufacturing. Parkhurst opened his talk by stating that dimensional scaling, Moore’s Law, is still very much alive and well despite reports to the contrary. He showed a timeline for Intel IC production showing a very regular, 2-year clock tick on dimensional scaling at Intel: 90nm in 2003, 65nm in 2005, 45nm in 2007, 32nm in 2009, and forecasting 22nm in 2011. Interesting, but not news—perhaps.

What was news to me was the huge change in lithography that has occurred in the jump from 65nm to 45nm and 32nm. Here’s the slide that crystallized this thought for me:

As you can see, we were having all sorts of problems making reasonable patterns at 65nm. Wires thinned dangerously, to the point of almost disappearing. Edges and corners are rounded. At 65nm, the entire litho world looks more like a Salvador Dali surrealistic painting than the nice, regimented, map-like shapes we’ve come to expect. The chip patterns look melted.

Then…something happened. Look at the crisp lines at 45nm and 35nm. What gives? Note that the lines all run one way. A revolution took place in the way Intel lays out its chips. By restricting each layer to one direction, by sticking with uniform gate dimensions, and by enforcing a rigid and gridded layout, Intel has made the surreal lithography of 65nm vanish. (To get more detail, see Kelin Kuhn’s 2009 keynote presentation “Variation in 45nm and Implications for 32nm and Beyond” from the 2nd International CMOS Variability Conference in London. That’s where the above image was taken. Click here.)

“But,” said Parkhurst, “that’s the digital world.” Intel wants to leverage its success in the digital world by integrating digital, AMS (analog/mixed-signal), and RF components on the same die. “The opportunity to integrate is there,” said Parkhurst, “but there are costs.” It’s possible to use SiP (System in Package) technology to blend AMS and RF functions with digital circuitry, as discussed in my previous blog from the 8th International SoC Conference (“70% of re-spin issues are AMS in nature: How mixed-signal design can mess up a perfectly good SoC”) but that’s the least desirable option in Intel’s opinion because the unit cost for a SiP will be more than for a successful monolithic design. So Parkhurst and his team are looking into several options.

The first option is the use of stacked die (3D technologies). The second option is to figure out how to “do” less analog and more digital, moving the A/D and D/A converters closer and closer to the real world. Parkhurst’s team also seems to be considering some extreme circuit topologies such as sub-threshold and near-threshold circuits. The team is also looking at the possibility of synthesizing and verifying AMS components, so that they are correct by construction. Such automation will reduce or even eliminate the need for Spice simulations, which will significantly speed design.

The Intel team is also looking at more advanced pre-silicon validation schemes. For example, they’re considering the simulation of AMS blocks at higher levels of abstraction that fit well with Intel’s existing digital design flow. “What is the right level of macromodel to accurately represent component behavior?” mused Parkhurst.

About sleibson2

EDA360 Evangelist and Marketing Director at Cadence Design Systems (blog at
This entry was posted in EDA360, IP, Silicon Realization, SoC Realization and tagged , , . Bookmark the permalink.

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