Certainly one of the most interesting talks at the 8th International SoC Conference in Irvine last week was the keynote given by Raouf Halim, CEO of communications IC specialist Mindspeed Technologies. The talk had everything I like to hear: history; technology; engineering; and cold, hard reality. It’s not easy to roll all of that up in a 40-minute presentation but Halim carried it off.
First the history—it’s as relevant now as it was when it was being made. Dial yourself back in Mr. Peabody’s Wayback Machine to the year 1995 when Fax/Modem chips were the rage and the leading device was made by Rockwell Telecommunications (Mindspeed’s ancestor). (Man that seems like eons ago!) Back then, Rockwell was rocking the world with a 14.4 kilobit/sec modem chip in a 68-pin PLCC. However, it wasn’t a chip! Here’s a picture.
Today, we’d call this a 3D IC because inside of that PLCC is a carrier (called an “interposer” today) with four other chips mounted on it: two sigma-delta analog front end (AFE) chips, a controller (processor) chip, and a separate DSP. The total transistor count was nearly 3 million! Back then, it made sense to separate the analog silicon from the digital and it also made sense to keep the controller and DSP separate because, well, it was hard to get all of those transistors on one piece of silicon real estate and get a respectable, commercially viable yield at the same time.
Fast forward to today and—although the transistor counts have gone way up—the tradeoff considerations aren’t any different. It still makes sense to keep the analog components off of the high-density digital silicon because the analog parts really need a different process technology. It’s often cheaper to use multiple chips and glue them together with a low-cost packaging technology. These are exactly the sort of economic- and engineering-tradeoff calculations envisioned in the Cadence System Realization, SoC Realization, and Silicon Realization strategies.
Next, consider the changes that have taken place from 1995 to today. Chip complexity is way, way up thanks to Moore’s Law. But if you think silicon complexity is up, just take a look at the increase in software complexity:
In 1995, maximum chip complexity was something under 50 million transistors (way, way under in the case of the Rockwell Fax/Modem “chip”) and you needed fewer than 100,000 lines of code to run the silicon. In 2005, Mindspeed’s VOIP chip required 300 million transistors and 2 million lines of code. In ten years, from 1995 to 2005, transistor count went up by a factor of six or so and software complexity rose by 20x! Looking at the current requirements for an LTE baseband chip, Mindspeed sees the need for a chip with more than 700 million transistors (barely 2x more than for a VOIP chip) but 20 million lines of code. That’s 10x more code than the VOIP chip and 200x more code than for a Fax/Modem chip.
So what’s the implication? Well, said Halim, for every 10 hardware design engineers you now have developing an SoC you need 20 verification engineers (twice as many verification engineers as design engineers) and 200 software developers to write all that code. You need 20 software developers for every hardware design engineer. That statement and the slide below neatly encapsulate the thinking behind the Cadence EDA360 vision.