Need really big FPGAs? Xilinx will be taking the “3D” route for initial Virtex 7 parts

Ivo Bolsens, the Xilinx CTO and Senior VP, presented a keynote at the 8th International SoC Conference a couple of weeks ago and one of the aspects of FPGA development that he discussed was Xilinx’ plan for creating large-capacity Virtex 7 FPGAs using 28nm process technology. Every leading-edge process technology experiences a learning curve and initially, it’s hard to make the largest possible chips in any new process technology with commercially viable yields. So Xilinx faced a problem: it would not be able to make the largest possible Virtex 7 FPGAs for a while using 28nm technology. What to do for those leading-edge customers who always want to use the largest, fastest parts as soon as possible?

The answer, as far as Xilinx is concerned, is 3D technology. Poke anywhere in the chip-design industry these days and you will find very active discussions of 3D chip packaging. I first wrote about 3D technology in 1988, so it’s not like this is some new technology looking for a home. In fact, a form of 3D technology has become commonplace already. Nearly every mobile phone handset incorporates a packaged integrated circuit consisting of a stack of silicon die wire-bonded to each other and to the package. Yes, it’s a Rube Goldberg approach to high-tech silicon interconnect, but it just happens to be a widely used packaging technology in consumer products manufactured in the highest production volumes today. Such is the paradox that 3D proponents are addressing with their plans to bring 3D chip-packaging and assembly into the 21st century.

From Xilinx’ perspective, 3D packaging solves several significant problems in the manufacture of large, leading-edge FPGAs. The first such problem is the sheer number of I/Os you get when you partition an FPGA, which are essentially more than 90% interconnect and perhaps 10% logic. If you slice an FPGA die anywhere, all you’ll likely see is wires. So assembling a large FPGA from several FPGA slices requires an interconnect technology that can handle high-density I/O. Wire bonds are not appropriate for such densities.

Next, the interconnect bandwidth of those many, many I/Os will serve as the major performance constraint on any hybrid FPGA’s overall performance. So the selected high-density interconnect technology must have low inductance and low capacitance, which will both improve the interconnect’s bandwidth and will drive down the amount of power consumed by the many required I/O drivers. Wire bonds are simply not in the running here either.

Xilinx has chosen “2.5D” interconnect technology to attack these problems. The company has created Virtex 7 FPGA slices that are designed to be mounted to an I/O-rich passive silicon interposer to create a large FPGA. Apparently, Xilinx has been developing this technology for years and has decided that the 28nm Virtex 7 FPGA generation is the right time and place to roll out this technology.

The silicon interposer is thermally matched to the silicon FPGA slices and it offers 20x the I/O density of ceramic interposers. The result: 10,000 die-to-die connections using a 65nm process technology to fabricate the entirely passive interposer. (It’s just silicon and metal.) Here’s an image of how the whole thing fits together:

If you’d like more information on this technology, Xilinx recently published a white paper about it. Click here.

Note: IC packaging and 3D technologies are very much a part of the EDA360 vision and the Cadence Silicon Realization product line. You can’t Realize a chip without the package.

About sleibson2

EDA360 Evangelist and Marketing Director at Cadence Design Systems (blog at
This entry was posted in EDA360, Silicon Realization and tagged , , . Bookmark the permalink.

Leave a Reply

Fill in your details below or click an icon to log in: Logo

You are commenting using your account. Log Out /  Change )

Twitter picture

You are commenting using your Twitter account. Log Out /  Change )

Facebook photo

You are commenting using your Facebook account. Log Out /  Change )

Connecting to %s