Normally, I don’t post responses to my blog discussions on LinkedIn Groups, but I think Nalini Patel’s comment on my recent blog entry about the IP Roundtable discussion at the Low-Power Engineering Community is worthy of its own blog entry. Patel is a Global Technical Applications Manager at NXP Semiconductors in Stevenage, UK, so I’m guessing she’s fairly up to speed on IP issues. She certainly writes like she is very familiar with IP. Patel wrote:
“I agree with Gianfagna, it takes a lot of investment to build IP which you could hold up and say you believed in it 100%. I have to disagree on the quality aspect though, I think it is more a case of not clarifying the conditions, under which it functions/has been validated, clearly enough.
IP integration takes a huge effort, even when it works and that is part of the problem. There is NO plug and play IP out there, no matter what anyone says. However, when management say ‘IP’ they often think it is plug’n’play, That’s putting it simply,and I am sure that none of them ACTUALLY think it is true, however the effort estimation is wildly out for building the SoC.
There is huge value in IP, estimating integration better would be even more valuable in this market though.”
The shift towards commercialized IP is a huge course change for Cadence and is a fundamental part of the EDA360 vision. This course change represents Cadence’s agreement with Patel’s statement, “There is huge value in IP.” Simply put, SoCs cannot be designed without it. Therefore, it must have value.
Having been deeply involved with semiconductor design and verification IP for the last 10 years, I certainly agree with much of what Patel writes. I too believe there’s a lot of high-quality IP out there, although perhaps not all of it attains the quality level we’d prefer to see.
When Patel writes “There is NO plug and play IP out there” I tend to agree, but then I need to ask: “Why is this so? Don’t we want to change this situation? Can we?”