New Cadence White Paper on 3D IC design with TSVs (through silicon vias). Are you ready for this? Are you sure?

Richard Goering’s blog “Whitepaper: 3D ICs Pose Design Challenges, But No ‘Showstoppers’” summarizes a new Cadence White Paper on 3D IC design. As Richard writes, “3D ICs with through-silicon vias (TSVs) promise tremendous power, cost, and size advantages, but they also generate a lot of concern about what’s required in terms of design flows, skills, and tools.” Richard’s blog entry will give you the tip of the iceberg. If you want the whole iceberg (White Paper), click here.

About sleibson2

EDA360 Evangelist and Marketing Director at Cadence Design Systems (blog at https://eda360insider.wordpress.com/)
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