Re-capping the de-cap bottom line on chip/package/board co-design. What the heck is “Spray and Pray”?

Design intent is a collection of information threads that permeate design from the chip to the package to the board to the system. That’s a basic EDA360 concept that underlies the desire to put more and more design-intent information into the design database so that all design tools can share this additional knowledge. Usually, this information remains undocumented and is therefore lost from one design stage to the next. Next month’s DesignCon 2011 at the Santa Clara Convention Center features a paper jointly written by authors at Cisco and Cadence about several facets of co-design using design intent. The paper is titled “Using Co-Design to Optimize System Interconnect Paths” and it discusses the advantages of being able to use design information simultaneously at the chip, package, and board level to—among other things—eliminate the perpetually occurring rat’s nests of wires we always see in transitions from die to package and from package to board.

Another facet discussed in this paper is the distribution of decoupling capacitors (de-caps) between IC package and PCB. The paper uses a term I’ve never seen, “spray and pray,” to discuss the insertion of decoupling capacitors on packages and boards. I may never have seen the term, but I sure am familiar with the design technique. It’s very, very old and dates back to the early 1970s when TTL ICs became king dinosaurs of design mountain. We knew that we needed to place a 0.1 μF ceramic de-cap beside each TTL package to combat noise on the 5V power rail. It was a rule of thumb. Unfortunately, there wasn’t always room for the de-caps so you only got partial adherence to this rule. You can see that in this circa 1976 photo of an I/O board for an HP 98036A HPIB interface card.

HP 98036A interface card processor board, designed by Dick Barney.
(Photo Copyright 2010, Steve Leibson, used with permission.)

You can see that there are plenty of de-caps on the left two thirds of the board—almost as many de-caps as there are ICs. You can hardly miss seeing those bright blue de-caps. However, on the right side of the board there aren’t so many de-caps. In fact, I don’t see any. (Note that the right side of the board is the processor side. Despite being designed way back in 1976, this design is an early embedded design that employed HP’s proprietary Nanoprocessor—the white chip with “-5.0 V” hand written on the top—designed and fabricated in Loveland, Colorado.)

The point of this image is that the de-caps were added using the “Spray and Pray” technique. The engineer added as many de-caps as space allowed and if there were no power supply problems then the design was deemed sufficiently robust. There was no design information available about whether each of these TTL packages needed a de-cap. The caps were cheap, so we sprinkled them on the board liberally where we could.

That’s not how things work today. In miniaturized equipment such as mobile phone handsets, we value every square mm of board space and can’t afford to waste even milli-pennies on unneeded de-caps. We have models that tell us what happens to the power supply when a chip’s I/O drivers switch on. We have or can derive resistive/capacitive/inductive analog models of the power distribution networks on chips, packages, and boards. None of this information is contained in the RTL descriptions or schematics that normally constitute design documentation. However, that information is very useful when developing an engineering approach to de-cap distribution. Co-design methods increasingly rely on information like this.

To learn more about co-design, consider attending next month’s DesignCon.


About sleibson2

EDA360 Evangelist and Marketing Director at Cadence Design Systems (blog at
This entry was posted in EDA360, Packaging, SoC Realization, System Realization. Bookmark the permalink.

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