Can you really value SoCs in dollars per square centimeter?

EETimes just posted an article written by European editor Peter Clarke with an interview of Malcolm Penn, founder of and principal analyst with Future Horizons. Penn notes that 4Q 2010 shows the first semiconductor fab capacity growth in six quarters and that IDMs are increasingly relying on foundries to make chips rather than adding native IDM fab capacity. He then notes that TSMC has raised their prices as a direct result of the industry’s growing dependence on TSMC’s output so that the company wishes to be “paid full value for all the risk investment they have made.” “They are tired of being paid $4 per square centimeter of silicon when their customers get paid $9 per square centimeter,” he says.

I got a chill when I read that last sentence because it strikes at the heart of the EDA360 vision. If you take that statement at face value, then you understand that chip vendors will be paid on the basis of square silicon area no matter how much effort, ingenuity, and unique IP they put into the SoC. Now this summary may be somewhat of an exaggeration but it underscores the very real point that chip profits are not tied just to the silicon any more. Half of the cost of developing an SoC is tied up in creating software or firmware that runs on that SoC. Half the cost and perhaps a disproportionate share of the margin as suggested by the dollars-per-square-centimeter metric.

This is today’s legacy from Moore’s Law. We’ve reached the point in semiconductor development where we can freely use processors to implement many of the functions previously implemented in hardware. This change represents an architectural revolution similar to the system-level microprocessor revolution that occurred in the ten years following the release of the first commercial microprocessor in 1971. Prior to 1971, there really was no such thing as an embedded system. Unless you planned on bolting a minicomputer into your system, you designed everything in hardware. There was no firmware because there were no small processors to run that firmware.

Until about 1995, the same was true for ASICs. There just wasn’t enough on-chip gate capacity to justify placing a processor on the ASIC. If you needed a processor, you bolted a microprocessor chip to your ASIC. Then 1995 ushered in the era of the SoC (an ASIC with one or more on-chip processors) and firmware suddenly became part of the design mix.

Where one processor appears, more are sure to arrive and quickly. The consequence: today’s SoCs sport half a dozen or more on-chip processors. Some SoCs have dozens of on-chip processors. A few have hundreds. As has been noted, SoCs are rapidly becoming software-execution machines. This software largely defines what the SoC does. Consequently, the software now largely defines the SoC’s value to the end customer. This situation doesn’t make the silicon less important. No silicon, no software-execution engine. However, it’s clear that a comprehensive approach to SoC design tools simply cannot ignore software development for that SoC. Neither can EDA companies ignore the importance of offering or supporting software-development tools that work hand-in-glove with the tools of Silicon Realization.

About sleibson2

EDA360 Evangelist and Marketing Director at Cadence Design Systems (blog at https://eda360insider.wordpress.com/)
This entry was posted in EDA360, IP, Silicon Realization, SoC Realization, System Realization. Bookmark the permalink.

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