Eric Esteve, owner of IPNest—an IP market research company in Paris, has written a review of the IP-SoC event held in Grenoble late last year. If you’re not familiar with the IP-SoC event, it’s been held for several years now by Gabriele Saucier and her Design and Reuse organization. The insights Eric gleaned from the IP-SoC conference are pretty interesting, and I’ll summarize them and the extremely salient comments to his post.
First, Eric addresses the question of IP growth, atopic covered in a keynote by Ganesh Ramamoorthy, Principal Research Analyst at Gartner. Ramamoorthy’s numbers say that IP sales jumped nearly 25% from 2009 to 2010. Ramamoorthy broke that overall number down as well: IP licensing representing 50% of total grew by 20%; royalties representing 42% of the total grew by 31% and maintenance/services representing 8% of the total grew by 25%. The high growth of the royalty segment represents the oncoming wave of SoC production that now incorporates a substantial amount of purchased IP.
One of Ramamoorthy’s noted trends as described in Esteve’s blog entry read as though they were lifted from the EDA360 vision document published by Cadence (available by clicking on the link to the right of this EDA360 Insider blog entry):
“Innovation is moving from chip level to system level was the clear message. Or, if you prefer, be prepared to provide not only a piece of H/W to be used within a chip, but a more complete solution integrating several pieces of H/W, the drivers for these, and the S/W at system level.”
In the SoC Realization universe, IP cannot just be some packaged RTL. Successful IP requires a multilevel set of descriptions including the RTL, physical IP for high-speed interfaces and analog, verification IP, documentation, and software including drivers and applications. Without the full IP stack, commercial IP cannot hope to save the design team as much development cost as desired.
Bill Martin, VP at E-System Design, provides additional deep insight in a comment he makes to Esteve’s blog entry:
“The next phase to subsystems will be to create physically laid out (Digital + Analog) per various process nodes. Additional planning for these blocks will be required to allow user to easily enable/disable functionality that is contained within the hardblock with either hard wired or programmed registers.
With the ‘common’ foundries, this is easier and cheaper to implement. This will be driven from several perspectives: first the speeds that these blocks are reaching will continue to require very tight control over layout and synthesis; second IP vendors will determine that support costs are too great for the speeds required along with ‘minor’ tweaks that are performed by users; third, physically laid out will enable better protection of IP rather than RTL/C code; and when available, 3D TSVs will be another opportunity to create IP subsystem dice for use in heterogeneous SoP/SiP solutions.”
It’s worth your time to take a look at the full blog and the insightful comments.