Many years ago, in the late 1980s, while returning to our home in Boulder, Colorado from a holiday trip to Seattle, Washington, my family and I stopped off in Boise, Idaho just after New Year’s day so I could visit the headquarters of Micron Technology, a scrappy memory maker trying to dominate the brutal semiconductor memory market from a most unlikely place, the land of the Idaho potato. I was struck during the visit on how self-reliant Micron was—due to its far remove from Silicon Valley. There were pieces of fab and testing gear in the hallways awaiting modification and adaptation to the next process node. Work that Micron’s techs would perform themselves. Now that’s self reliance and that self reliance must be—at least in part—why Micron is still very much in the game while other contenders (too many to name) have ceased to compete. So I read with great interest the few words Micron president and COO Mark Durcan gave to EE Times Europe (see Micron COO talks 450-mm, 3-D, EUV).
One of the first things that jumped out from Durcan’s comments was the statement that mass production of 3D ICs with TSVs (through-silicon vias) was no more than 18 months away, possibly only 12 months away. Several in the industry are calling 3D IC assembly a way to attain “More than Moore” integration. I think that’s a stretch (Moore’s Law strictly applies to monolithic silicon chips, but whatever). However, I do think that 3D assembly will be a very important development for the industry, once we work out the bugs. And believe me, I’m looking forward to the work on 3D bug eradication because it will take a lot of EDA assist, and don’t think we aren’t acutely aware of that here at Cadence.