Wednesday, I attended the Common Platform Technology Forum 2011 held at the Santa Clara Convention Center. The Common Platform is an alliance among IBM, Samsung, and GLOBALFOUNDRIES to develop new, ever-more-advanced IC process nodes. The alliance is currently moving the 32nm node into production, with 28nm being a planned shrink of the 32nm process. The combined fab capacity of the Common Platform Alliance members exceeds that of other silicon foundry players, which is the Alliance’s way of saying “Together, we’re bigger than TSMC.”
One of the announcements made during the Forum was that the Common Platform Alliance was sticking with gate-first, high-K metal gate (HKMG) technology for the 32nm and 28nm nodes. That’s not news. What was news, I guess, is that the Alliance plans to use gate-last HKMG processing for the 20nm node. In the world of semiconductor process technology, this is news because gate-first versus gate-last HKMG has been debated for years. IBM and the Common Platform Alliance partners have been solidly in the gate-first camp. Intel and TSMC have been in the gate-last camp. (See Richard Goering’s blog on this topic: “Common Platform Forum: A Clearer Path to Advanced Process Nodes”).
Two camps means there’s a controversy, for those who care about this particular topic. It makes for a good news story anyway.
The Common Platform announcement of its plan to adopt gate-last HKMG processing at the 20nm node comes from an economic analysis of the costs associated with the double-patterning lithography required at the 20nm node. Double patterning changes a lot of the basic assumptions built into process-technology economics.
I’m not going to get into the esoteric particulars of the process-step differences between gate-first and gate-last HKMG. There’s plenty of online info if you Google it. Neither am I planning on furthering the gate-first/last debate here. It’s enough for me to hear that the Common Platform Alliance is choosing gate-last HKMG for the 20nm node because the Alliance’s economic analysis shows that the transistor density and fabrication costs favor the gate-last approach at that process node.
The real reason I’m writing this blog is because the same day I attended the Common Platform Technology Forum, I also attended a dinner for the Hot Chips (http://www.hotchips.org/) organizing committee at the Bella Vita restaurant in Los Altos, California. (Great food, by the way.) At the dinner, one of the organizing committee members asked me if I’d heard the big news at the Common Platform event. He was referring to the 20nm gate-last announcement. It was big news to him.
“It must deserve a blog entry,” I thought because I suspected that the choice of gate-first versus gate-last gets abstracted away by the Process Design Kit (PDK) so it’s not such a big deal for most Silicon Realization teams. I tested that suspicion by asking around and got this statement from Robert Makofske, Customer Engagement Director here at Cadence. Here’s what he wrote to me:
“PDKs, of course, provide the correct models, layouts, and verification IP to address either choice.”
And that’s the point of this blog entry. The fabs (or the fab alliance in this case) are responsible for making the right process-technology choices to give Silicon Realization teams the best bang for their money. EDA companies like Cadence are responsible for working hand-in-hand with the major fab vendors to transform those process-technology choices into EDA tools and tool components like the PDKs that maximize the Silicon Realization teams’ ability to design chips and get them fabricated in the most expedient, most efficient manner possible, no matter what process technology each team targets.