Last week, the Common Platform Alliance—consisting of IBM, Samsung, and GLOBALFOUNDRIES—held a Technology Forum at the Santa Clara Convention Center (SVCC) to discuss its 32/28nm process nodes now going into production (the 28nm node is mostly a straight shrink of the 32nm process node), the 20nm process node, and future plans for more advanced semiconductor-processing nodes. The keynotes and initial panel discussion took place in the SVCC’s 22,400-square-foot ballroom, which can hold as many as 3199 people when set up in a theater arrangement. I didn’t see 3000 people in the room, but it was clearly more than 1000 and it certainly felt like more than 1000 in the lunch queue. The place was packed. The keynotes were pretty darn good. It all put the Common Platform Alliance in a very professional light.
Last week, I wrote about the Alliance’s announcement that it would be switching from gate-first to gate-last fabrication in the transition from 32/28nm to 20nm. I also wrote that such a change was mostly of interest to process geeks, because Process Design Kits (PDKs) from EDA companies like Cadence pretty much abstract such details and make them invisible for the rest of us. That is, after all, one of the reasons that PDKs exist in the first place. Also, I’d be foolish if I didn’t mention (yet again) that abstraction at multiple levels is a fundamental tenet of the EDA360 vision.
I mentioned last week but did not emphasize one of the Forum’s main messages: together, the Common Platform Alliance has more fab capacity than any other fab vendor, a clear and not-very-oblique reference to TSMC. According to Semico data projected during the keynote, the Alliance has a combined annual fab capacity of nearly 400,000 200mm-equivalent wafers in 2011 versus TSMC’s 200,000. Based on the increased capex (capital expenditures) made by the foundry vendors thanks to booming sales in 2010, Semico projects that the Alliance’s fab capacity will exceed 1,000,000 200mm-equivalent wafers in 2012 and about 1.7 million 200mm wafer equivalents in 2014, versus 700,000 and 1.35 million for TSMC in 2012 and 2014 respectively. There’s a lot of new capacity going on line, which means that the ravenous maw of the semiconductor industry needs to be filled with successful new, high-volume designs.
By numeric comparison alone, the Common Platform Alliance makes a credible competitor to TSMC. However, aggregate volume numbers don’t always tell the whole story and certainly don’t here. As Daniel Nenni points out in his recent blog entry “TSMC Versus The FabClub!”, the members of the Common Platform Alliance are GDSII and DRC compatible, but not mask compatible, so you’ll need new masks to go from one vendor to the next. Does that matter? Maybe. Depends on what you’re looking for.
EDA360 Insider 