The advent of gate arrays opened the gates of custom silicon for everycompany. Before that, only the really heavyweight players could afford the tools and training to create tailored ICs for their end products. The early gate arrays changed that situation by lowering costs to the point where custom silicon made sense in far more system designs. In a sense, we’re facing the same situation today. The cost of creating an SoC or ASIC in 65nm, 40nm, and now 32nm process technology has climbed to the tens of millions of dollars. It’s a game not everyone can play for a variety of reasons.
One of those reasons has to do with NRE versus run rate. If the NRE to develop a chip is in the tens of millions of dollars and if mask costs are a few million dollars, then you need to sell many, many millions of chips using that one design to recoup the design costs. Very few applications in even fewer markets qualify with the required stratospheric run rates.
Another of those reasons has a lot to do with risk. The risk of failure on first-pass silicon can be severe. Some markets are so unforgiving that you don’t get a second chance with conventional fabrication delays. A design error means a missed market window and total project failure. Another way to say that is “high risk.”
The Microsystems Technology Office (MTO) of the US Defense Advanced Research Projects Agency (DARPA) is in a similar situation when it comes to developing advanced chips. Run rates for advanced military chips rarely reach the volumes needed for practical development of advanced ICs. As a result, DARPA’s MTO is managing a project that takes a new tack on an old idea: direct-write e-beam lithography. The program is called the “maskless nanowriter” and it’s being developed by KLA-Tencor under a DARPA contract. The Nanowriter’s goal is to make small-lot fabrication of imaged wafers practical.
Earlier this month, DARPA issued a press release detailing the current status of the project. The press release details two milestones: “This DARPA program recently achieved two important milestones when it demonstrated a micro-lens array to pattern a beam into a million electron beamlets and showed a second-generation eBeam column designed to significantly reduce pattern blur.” The press release doesn’t name the prime contractor, but you can see more information from KLA-Tencor about the Nanowriter in a 2008 Sematech presentation here.
The key to making something like the Nanowriter work is maskless exposure. Early work on direct-write e-beam lithography stretches at least as far back as the early 1980s when Cray Laboratories in Boulder, Colorado (an offshoot of supercomputer pioneer Cray Research) attempted to convert Cambridge-brand electron microscopes into direct-write exposure machines. Back then, the goal was not mask-cost or risk reduction but speed. Cray wanted to be able to turn chip designs quickly, so that the company could explore different architectural designs. However, the relatively small electron microscope beam current and insensitivity of the resists available at the time doomed the project. Three decades later, things appear to be different.
Even if DARPA’s Nanowriter succeeds in making masks superfluous, there is still the design cost of a large SoC to contend with. Mask costs may be high, but they still represent only a small fraction of the overall chip-development cost. The rest of cost and risk must be addressed by creating well-integrated EDA flows that dovetail with this different approach to making advanced ASICs.