How about a couple more bits on Design Intent from an EDA360 perspective?

It’s often hard to describe what terms mean in the fluid, galloping world of EDA. Design Intent, one of the “big three” design legs of the EDA360 vision (which also encompasses Design Abstraction and Design Convergence) is hard to nail down to specifics because there are so many facets to intent. In the past, I’ve discussed power intent using the CPF specification and also pinout intent to help align chips, packages, and boards and to reduce complex routing problems that arise when pinout intent isn’t communicated up and down the design chain. Today, Cadence announced a new, validated Digital End-to-End flow with two more examples of Design Intent: clock topology intent and design-rule intent. Often, these design parameters were passed around using a spreadsheet because the design tools didn’t accommodate this sort of design information. Yet to ignore the information is to explicitly choose sub-optimal design. Hence the ad-hoc adoption of spreadsheets.

The EDA360 vision says “Dispense with the spreadsheets.” Instead, don’t you think it’s a better idea to get this design intent into the common design database and then make that information freely available to all of the design tools. Yeah, us too.

That’s part of what’s behind today’s announcement. Sure, it works with 28nm. In fact, it’s already proven there. However, not everyone is willing to sign up for the 28nm node just yet. What about them? Well, though it should be intuitively obvious, this new digital flow works with the earlier nodes too. Things work faster than they did. Things work better than they did. For everyone.


About sleibson2

EDA360 Evangelist and Marketing Director at Cadence Design Systems (blog at
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One Response to How about a couple more bits on Design Intent from an EDA360 perspective?

  1. Mike Eneboe says:

    Maintaining design intent (DI) throughout the entire design flow is critical. EDA360 is doing a great job of evangelizing this (if this is not understood by everyone, then keep working on them). In addition, the level of “abstraction” of DI also needs to be raised. The tools need to be given as many degrees of freedom as possible to meet the layout, power, area, affinity, timing and other DI goals. Goals for particular IP blocks should be raised to abstractions like “10Gbits of throughput, 100ns of latency, 1mW power”, etc. If you carry these kinds of abstraction through the design, then the tools will be able to adjust the design completion along the way, yet maintain the DI at the highest level of the design.

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