Since this morning, the Web has been abuzz with Intel’s announcement of the Cougar Point chipset that accompanies the company’s Sandy Bridge Core i5 and Core i7 quad-core processors. Propelled by estimates of a $700 million hit to someone’s bottom line, these kinds of headlines are attention-getting. Hence the ‘net buzz. For a saner, more detailed analysis of issue, you can turn to Semico’s Tony Massimini, Chief of Technology, and his blog entry in Semico Spin.
Essentially, writes Massimini, there’s one transistor in the 65nm design that’s causing the problem. Accelerated life testing indicates that this transistor might fail within 2 to three years. The transistor is in the legacy SATA port, which affects the chip’s SATA ports 2 through 5. So there’s no problem at all for systems designed to use only the faster SATA ports. For the rest, Intel expects to turn the chip around (only a metal layer needs fixing) and have revised parts shipping by April. Intel’s press release about this issue states that the shipping delay will “…reduce revenue by approximately $300 million…” for 1Q 2011 and “Total cost to repair and replace affected materials and systems in the market is estimated to be $700 million.” As Massimini says, these are worst-case-scenario numbers. In all likelihood, writes Massimini, “Semico does not see this delay as having a major impact on final end of year shipments for Sandy Bridge systems.”
So what’s the EDA360 take here? Intel is a leading semiconductor design powerhouse. The fact that the company caught the latent design problem so early is a testament to the company’s attention to detail and to the reliability lab that nipped this problem in the bud before it spread. Problems like this, and the large estimates of financial impact, underscore the need to be ever vigilant with all forms of verification. Every chip-design house is rolling a big pair of dice with each new chip, and it pays to be doubly and triply thorough.
Invite Murphy to visit at your own peril.