If your team is designing an SoC today, it’s no doubt a mixed-signal design. Every standard interface (think USB, SATA, etc.) now employs mixed-signal PHYs to reach out to the world beyond the SoC’s pins, not to mention the analog bits that make the world turn on every SoC such as PLLs, power-management circuits, and clock-tree drivers. Successfully taping out a mixed-signal design on schedule with the lowest possible power consumption and within budget is a big headache. How about some help? How about some relief? How about lunch? All for free.
Cadence is conducting several full-day technical seminars in 15 locations around the world where you’ll learn from mixed-signal Silicon Realization experts. They’ll tell you how to successfully realize today’s highly integrated and complex mixed-signal designs more productively and profitably (within budget and on schedule). You’ll hear real-world case studies of successful designs that achieved their tape-out goals, optimized performance and power, reduced design and manufacturing costs, improved turnaround time, and mitigated functional and quality risks.
They did it and you can as well.
Plus there’s lunch. Free. Did I mention that already?
The events take place from February 17 to March 17 and there are unfortunately only a limited number of seats, so you need to register now, here.
Why are you still here?