ARM furthers its “cover the earth” strategy with introduction of R5 and R7 core variants for fast, real-time, deterministic SoC applications

Not at all content to be the world’s largest supplier of processor IP, ARM took steps last week to ensure an ever-expanding universe of ARM-powered SoCs by introducing two new cores in its Cortex-R series processor cores targeting real-time apps (that’s what the “R” stands for). The Cortex-R series ARM processors, including the previously announced R4 and the new R5 and R7 MPCore processors, sport features designed to enhance their use in real-time embedded applications such as automotive products, mass-storage peripherals, industrial controls, and baseband control for 3G and 4G cellular telephony and other wireless markets. The announcement for the R-series Cortex ARM processors emphasizes real-time and deterministic performance, which sets the R series apart from the other, larger A-series cores in the ARM stable that have been designed as big, general-purpose apps-execution engines.

ARM Cortex-R5 MPCore processor block diagram

Two features that ARM believes suit the R-series to mobile baseband designs are high-frequency interrupts and deterministic control of data transmission through a new, low-latency peripheral port (LLPP) that’s essentially a dedicated, 32-bit AMBA (AXI with optional AHB) port designed to connect latency-sensitive peripherals more tightly with the processor. There’s also an accelerator coherency port (ACP), which is a 64-bit AXI slave port that permits coherency between the processor (or processors in the case of a multicore R-series processor) and external intelligent peripherals such as DMA controllers, Ethernet ports, or Flexray interfaces.

ARM Cortex-R7 MPCore processor block diagram

For high-reliability industrial, automotive, and medical applications, the new R-series processors provide features to support hard- and soft-error management, redundant dual-core configurations, and ECC on all external buses. Both the Cortex-R5 and -R7 cores can be implemented in dual-core configurations for lock-step, redundant computing and the Cortex-R7 processor core incorporates ARM’s existing A-series SMP technology. The Cortex-R7 processor core also implements more advanced, performance-oriented processor architectural features such as out-of-order (OOO) and superscalar instruction execution, dynamic register renaming, enhanced branch prediction, and a hardware divider. The ARM release makes it clear that the larger Cortex-R7 MPCore processor is aimed primarily at leading-edge, 28nm SoC designs.

Notably, all of the R-series Cortex processor cores including the previously announced Cortex-R4 processor core are binary backwards-compatible with the ARM7, ARM9, and ARM11 processor instruction sets. This backwards compatibility allows the processors to run existing and type-certified code without recompilation—a feature that’s required in many regulated application markets such as cellular telephony, automotive, and medical equipment.

ARM says that four tier-one licensees have Cortex-R5 or -R7 designs underway, destined for the mass-storage, automotive, and mobile baseband markets. One application niche the ARM release doesn’t mention is use of these new cores in the FPGA arena. Both Xilinx and Altera have announced that they will be introducing new IC families that merge hard-core processors with FPGA fabrics this year. Both companies have discussed using ARM A-series Cortex processor cores in these designs. However, the new ARM Cortex-R5 and -R7 processor cores offer some very enticing features that make them ideal mates for FPGA fabrics—notably their dedicated, fast, deterministic, peripheral ports. We’ll be anxious to see if ARM’s new R-series announcements cause any FPGA ripples.

About sleibson2

EDA360 Evangelist and Marketing Director at Cadence Design Systems (blog at https://eda360insider.wordpress.com/)
This entry was posted in ARM, EDA360, SoC Realization. Bookmark the permalink.

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