Fully-Depleted SOI: Is it the light at the end of the nanometer Moore’s Law tunnel? Building a high-performance, low-power ARM processor core with 20nm FD-SOI

Last week, EDN’s Ron Wilson wrote an article that discusses a significant announcement about 20nm SOI IC fabrication from the SOI Consortium (consisting of ARM, GLOBALFOUNDRIES, IBM, STMicroelectronics, Soitec, and CEA-Leti).  The announcement concerns the construction of a 30K-gate ARM Cortex-M0 processor core prototype vehicle using fully-depleted SOI (FD-SOI). Test results from this prototype vehicle are very encouraging.

The ARM Cortex-M0 processor core implemented in 20nm bulk, low-power CMOS delivers a 25% performance gain compared to the previous fabrication node, but 20nm FD-SOI delivers an 80% performance gain. In addition, tests show that memory cells implemented in 20nm FD-SOI CMOS are stable with a lower supply voltage than for bulk CMOS, 150mv lower. That drop in supply voltage represents an additional power savings of as much as 40% made possible with FD-SOI fabrication.

About sleibson2

EDA360 Evangelist and Marketing Director at Cadence Design Systems (blog at https://eda360insider.wordpress.com/)
This entry was posted in ARM, EDA360, IP, Silicon Realization. Bookmark the permalink.

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