Asynchronous FIFO design disaster forces silicon respin. A cautionary SoC design tale from the trenches.

Dealing with asynchronous clocks is like trick-or-treating on a dark and stormy night in a spooky neighborhood: the environment is full of hidden demons and monsters. Today’s blog post from Cadence’s Tom Anderson (The Tale of the Silicon Re-Spin and the Bug That Got Away) perfectly captures the terror that rises out of the earth when a design bug slips past and forces a silicon respin. Be sure to click on the link and read the blog post because it teaches a valuable lesson worth literally millions of dollars at the cost of less than five minutes of your time.

Although Tom doesn’t mention it, the bug appears because of a disastrous assumption made by the FIFO designer. I’m sure you’ll see that assumption. Now consider this: What if the design flow captured that assumption and what if the EDA tools could then test that assumption. Design assumptions are typically bug magnets and generally need to have beacons attached to them to draw special attention from verification tools.

Steve Leibson
EDA360 Evangelist

About sleibson2

EDA360 Evangelist and Marketing Director at Cadence Design Systems (blog at
This entry was posted in EDA360, SoC Realization, Verification. Bookmark the permalink.

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