Semico reports that ASICS, ASSPs, SoCs, and core-based ICs comprise the fastest growing category in MOS logic chips

EDA360 Insider followers will not be surprised to hear that Semico’s latest blog entry on Semico Spin claims that “Special Purpose Logic”—consisting of ASICS, ASSPs, SoCs, and core-based ICs—is now the fastest growing category for MOS logic chips and has been for the past decade with a CAGR of 12.3%. Why should this not be a surprise? Because these chips represent the ultimate incarnation of a system using just one chip for all the logic. You simply can’t go fewer than one chip. Fewer means zero. Nothing there at all.

For decades, the semiconductor industry’s main objective has been to fabricate an entire system on a chip and that’s what ASICS, ASSPs, SoCs, and core-based ICs do: they put an entire system (with the usual exception of big memories) on one chip. That’s the cheapest way to build the fastest system with the lowest power consumption, all other things being equal. It’s also interesting that this blog post specifically includes the phrase “core-based ICs.” In the world of “ASICs, ASSPs, and SoCs, you simply cannot build a chip that isn’t core-based any more. Cores include processors, DSPs, and accelerators (and there are more of them on chip every year); interface cores like USB, PCIe, and SATA; memory cores including SRAM, DRAM, ROM, and Flash; and memory-controller cores for off-chip memories.

In all of these cases, there are quality IP blocks available with appropriate drivers and verification IP so that it no longer makes sense to roll your own. That idea’s bound up in a “core” tenet of the EDA360 vision—SoC Realization—and Semico’s new blog post merely supports that view.

In fact, the Semico Spin post supports that view rather strongly:

“NRE (Non-Recurring Engineering) costs have always been an issue for ASICs, but the semiconductor industry has found ways to reduce this limitation for highly-integrated devices. One has been the re-use of blocks of logic, spreading NRE across several designs. A second has been the use of IP (Intellectual Property), blocks of logic designed by small, independent companies. By selling their IP to multiple parties, these companies can, again, spread the NRE across several designs. Purchasing IP from an IP vendor has an added benefit. Design engineers can add functionality beyond their own expertise or experience.”

This Semico Spin blog post was written by Morry Marshall, VP Emerging Technologies. Morry has been following this industry for a very long time so if he’s put his finger on a trend, you can tend to believe it’s real.

Steve Leibson, EDA360 Evangelist

About sleibson2

EDA360 Evangelist and Marketing Director at Cadence Design Systems (blog at https://eda360insider.wordpress.com/)
This entry was posted in EDA360, IP, SoC Realization and tagged , , . Bookmark the permalink.

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