Want 40% better SoC performance with 30% less power consumption? Mentor’s Wally Rhines says look to System Realization (without using those words) in his DVcon 2011 keynote

Mentor CEO Wally Rhines stood in front of the DVcon 2011 audience yesterday, delivering his keynote speech and said “The entire population of India will need to become verification engineers” if current trends continue. A shocking assertion perhaps, but one that Rhines has made before. He prefaced this statement with another, much earlier prediction that framed his verification statement. In that earlier prediction about 100 years ago, a statistician for the Bell Telephone System forecasted that at then-current rates of increase, every woman in the United States would have to become a telephone operator. Technology in the form of automatic dialing and stepping switches intervened and that employment prescription never came to pass. Neither will the one about verification engineers, said Rhines.

Rhines’ remarks are all predicated on a new Functional Verification survey commissioned by Mentor Graphics and conducted by the Wilson Research Group. This survey was conducted using the same format as surveys done in 2002 and 2004 by Collett International. Here are the salient trends from the survey sequence:

  • Verification engineers now account for most of the growth in today’s SoC design teams.
  • On average, there’s been a 58% increase in the number of verification engineers working on SoC projects.

Hence the prediction about India’s employment prospects over the next 50 years.

That’s just not going to happen, said Rhines, for a variety of technology-related reasons.

First, SoC designs are getting more complex a lot faster than they were in 2007. There’s a clear movement to smaller and smaller design geometries, but not just for cost reasons. Coincident with that trend is a big uptick in SoC designs with design complexity exceeding 60 million gates.

Yet in spite of that growth in complexity, first-pass design success has stabilized—at the somewhat disappointing number of 30%. Based on the survey findings, Rhines credits several verification methodologies with holding the respins at bay: increased code coverage, increased functional coverage, assertions, and most recently an uptick in the use of hardware-assisted acceleration and emulation.

Welcome to the brave new world of 21st-century System Realization.

At 60 million gates, no one can question that the SoC design realm is full settled into the world of system-level design. At Cadence, we call that “System Realization.” These are complex systems, far beyond the ASIC RTL designs of the 1990s, in the pre-SoC days. At these complexity levels, all sort of opportunities for abstractions arise and, as Rhines said in his keynote, “Abstraction is fundamental to improved quality and schedule.”

Want a real example? Rhines gave one during his keynote and it’s a great one. He cited one case study where architectural- and system-level analysis led to a 3% improvement in cache hit rate. Doesn’t sound like much, does it? But that 3% improvement in cache hit rate translates into a huge reduction in accesses to main memory. Result: 40% better performance and 30% power reduction. Those are pretty big numbers.

This case study is a very simple example of System Realization that illustrates the power of system- and architectural-level design. And that is the secret of raising the abstraction level. It’s a much better way to design complex SoCs—and these days, they’re all complex. As we find more ways to automate what’s done manually, we have more time and brain power to spend on more creative design pursuits that hugely enhance an SoC’s capabilities.

 

About sleibson2

EDA360 Evangelist and Marketing Director at Cadence Design Systems (blog at https://eda360insider.wordpress.com/)
This entry was posted in EDA360, System Realization, Verification. Bookmark the permalink.

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