EETimes video of Xilinx Zync EPP shows that it takes six FPGAs to emulate one EPP

A pointer on led to some excellent videos from the Embedded World event in Germany last week. The videos are from the Xilinx booth at Embedded World and show the pre-silicon emulation boards Xilinx has developed for the Zynq EPP (Extensible Processing Platform) family. (See my earlier blog entry “Xilinx Zynq EPPs based on two ARM Cortex-A9s create a new category that fits in among SoCs, FPGAs, and microcontrollers“.)

Olaf Schiller, a field Applications Engineer with Xlinx GmbH, explains the EPP architecture and the emulation board in the video. There are six FPGAs on the EPP emulation board and five FPGAs are needed just to emulate the EPP’s hardened processor complex that consists of two 800MHz ARM Cortex-A9 processors, DRAM and NAND Flash controllers, and a slew of peripherals from UARTs to Gigabit Ethernet controllers. Each of the six FPGAs has a fan sink attached to it, so you get an idea of the amount of electrical power needed to emulate a 2W chip—and you can bet that the emulated ARM Cortex-A9 processors aren’t running at 800MHz even with all of that dissipated power.

Hardware emulation of a complex chip like a member of the Xilinx Zynq EPP family is now essential prior to tapeout. It’s the only way to run software on a processor-intensive chip design at any reasonable speed so it’s the only practical way to give the software team a head start in code development. You can do that with an FPGA board, as Xilinx has done here, or with a more comprehensive approach such as the Cadence Palladium XP hardware/software verification computing platform, which is an integral part of the Cadence System Realization solution—a part of EDA360.

You can see videos of the Xilinx Zynq EPP demo here

About sleibson2

EDA360 Evangelist and Marketing Director at Cadence Design Systems (blog at
This entry was posted in ARM, EDA360, IP, System Realization, Verification. Bookmark the permalink.

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