How many people does it take to design an SoC? – Redux. Building brains with processors.

Earlier this month, I wrote a blog entry about the number of people it takes to design an SoC. (See “How many people does it take to design an SoC? Perspectives from Ron Collett and the EDA360 Insider”.) Since then, I’ve attended DATE in Grenoble and Steve Furber’s keynote address titled “Biologically-inspired massively-parallel architectures—computing beyond a million processors” contained a brief discussion of this topic. If you aren’t familiar with Furber, he’s the ICL Professor of Computer Engineering at the School of Computer Science, Manchester University, UK and his CV sports a long list of impressive achievements. More important for this discussion, perhaps: Furber was the principal designer of the first ARM processor for Acorn Computers back in the 1980s and he’s been exploring many of the interesting things you can do with a simplified 32-bit RISC processor ever since. Furber’s DATE keynote provided an update on one of those interesting things.

Furber’s university team is trying to build digital analogs of the human brain using “massively” parallel processing. However, “massive” in this case translates to 18 processors on one chip—not small but not massive either. I’ll be discussing the technical meat of this fascinating keynote address soon, but for this blog post, I wanted to discuss how Furber’s SpiNNaker Project (http://apt.cs.man.ac.uk/projects/SpiNNaker/) team is building an 18-processor SoC with a toroidal network-on-chip (NoC) interconnect that permits any-to-any interprocessor communications. Each processor is a 200 million instructions/sec ARM 968 RISC processor that consumes 0.4 square millimeters of area and 20mW. The NoC is based on the Silistix self-timed high-speed on-chip interconnect, which Furber also had a hand in developing at Manchester University. The entire chip is designed to emulate the organic brain’s neurons, axons, synapses, and massive interconnectivity by digitally modeling the way that neurons inside the brain distribute information to other neurons via “spikes.” The project’s intent is to create a standard digital platform for brain researchers to use for their explorations and simulations of brain function. As the SpiNNaker site says “…we hope that our deep understanding of the engineering of complex asynchronous systems may be of use in the Grand Challenge of understanding the architecture of brain and mind.”

It’s truly a fascinating project and it’s one that explores some very sophisticated MPSoC concepts without pushing design out to the very bleeding edge of IC process technology.

Now designing an 18-processor chip with a sophisticated, self-timed NoC isn’t child’s play. Yet Furber said his team consists of “4 or 5” experienced grad students and a handful of less experienced students as the implementation team. I find this a stunningly low number for such a sophisticated design and it’s an indication of the kind of productivity you can now achieve with System and SoC Realization tools. Sort of resets one’s thinking about SoC design team size, doesn’t it?

About sleibson2

EDA360 Evangelist and Marketing Director at Cadence Design Systems (blog at https://eda360insider.wordpress.com/)
This entry was posted in Apps, ARM, EDA360, IP, Silicon Realization, SoC Realization, System Realization. Bookmark the permalink.

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