Yole Développement publishes a magazine/newsletter called “3D Packaging” and it devoted the November issue to Wide I/O, recently covered in two EDA360 Insider blog posts about a memory introduction from Samsung and a package of design and verification IP products from Cadence. Yole Développement’s article, written by Sally Cole Johnson, gives what appears to be a remarkably clear picture of the state of Wide I/O and 3D packaing today. Here are some quotes from the article [with my editorial comments in brackets] that that jumped out at me:
“…Samsung [world’s #1 DRAM vendor] hails the wide I/O and through-silicon via (TSV) combination as the ‘best of both worlds’ in terms of achieving performance and thin multiple-die stacks.”
“Elpida [world’s #3 DRAM vendor] has installed a production line at its Hiroshima Plant to develop SV and mass production technologies for multiple connections using TSVs.”
“The company [Nokia] plans to integrate wide I/O interface structures using TSVs for mobile phones [world’s #1 electronic product in terms of production volume] in volume by 2013.”
“As handheld devices become increasingly more sophisticated, applications are emerging that require much higher memory bandwidth, says Jeff Brighton, director of CMOS 3DIC technology development at Texas Instruments [maker of the highly successful series of OMAP mobile application processor platform SoCs]. However, fundamental power and thermal limitations remain the same as in today’s handsets… In a nutshell, the wide I/O interface allows us to reach a high bandwidth at an acceptable power consumption level for a cell phone.”
“’The key reason for driving wide I/O interfaces is lowering the device power while maintaiing the same performance and bandwidth requirements. In some cases, you can reduce the power from 10W to 4W,’ says Calvin cheung, vice president of engineering for application and design at Taiwan-based packaging and testing house Advanced Semiconductor Engineering.”
“The key driver behind wide I/O right now is that the mobile phone industry is embracing it as a solution to combine processors with memories, especially for high-end smartphones and connected devices. Smartphone market share has soared from less than 5% a few years ago to nearly 30% today.”
“Wide I/O is based on a highly parallelized interface with a relatively low memory frequency [data-transfer clock rate] of 200MHz. That means that more than 1100 connections [!] are needed to connect the logic die with the memory die. Such a high number of connections can’t be done through a traditional package, such as package-on-package (POP), where the ball pitch is in the range of 0.5 or 0.4 mm.” [quoting Yann Guillou in ST-Ericsson’s office of the CTO].
“Bottom line: The industry is clearly collaborating and targeting wide I/O standards. It’s only a question of timing now.”
Note: If you need to follow 3D IC developments closely or you’re convinced that you need to know more about the topic now, there’s still time to sign up and attend the 3D day at the Electronic Design Process Symposium being held in Monterey, CA on April 7 and 8. Check it out here and sign up here. [But hurry, time grows short!!!]
If you’d like to see the whole wide I/O article from Yole Développement , you’ll find it here.