More on wide I/O and 3D ICs: It’s coming. Are you ready? Need to buy a clue?

Yole Développement publishes a magazine/newsletter called “3D Packaging” and it devoted the November issue to Wide I/O, recently covered in two EDA360 Insider blog posts about a memory introduction from Samsung and a package of design and verification IP products from Cadence. Yole Développement’s article, written by Sally Cole Johnson, gives what appears to be a remarkably clear picture of the state of Wide I/O and 3D packaing today. Here are some quotes from the article [with my editorial comments in brackets] that that jumped out at me:

“…Samsung [world’s #1 DRAM vendor] hails the wide I/O and through-silicon via (TSV) combination as the ‘best of both worlds’ in terms of achieving performance and thin multiple-die stacks.”

“Elpida [world’s #3 DRAM vendor] has installed a production line at its Hiroshima Plant to develop SV and mass production technologies for multiple connections using TSVs.”

“The company [Nokia] plans to integrate wide I/O interface structures using TSVs for mobile phones [world’s #1 electronic product in terms of production volume] in volume by 2013.”

“As handheld devices become increasingly more sophisticated, applications are emerging that require much higher memory bandwidth, says Jeff Brighton, director of CMOS 3DIC technology development at Texas Instruments [maker of the highly successful series of OMAP mobile application processor platform SoCs]. However, fundamental power and thermal limitations remain the same as in today’s handsets… In a nutshell, the wide I/O interface allows us to reach a high bandwidth at an acceptable power consumption level for a cell phone.”

“’The key reason for driving wide I/O interfaces is lowering the device power while maintaiing the same performance and bandwidth requirements. In some cases, you can reduce the power from 10W to 4W,’ says Calvin cheung, vice president of engineering for application and design at Taiwan-based packaging and testing house Advanced Semiconductor Engineering.”

“The key driver behind wide I/O right now is that the mobile phone industry is embracing it as a solution to combine processors with memories, especially for high-end smartphones and connected devices. Smartphone market share has soared from less than 5% a few years ago to nearly 30% today.”

“Wide I/O is based on a highly parallelized interface with a relatively low memory frequency [data-transfer clock rate] of 200MHz. That means that more than 1100 connections [!] are needed to connect the logic die with the memory die. Such a high number of connections can’t be done through a traditional package, such as package-on-package (POP), where the ball pitch is in the range of 0.5 or 0.4 mm.” [quoting Yann Guillou in ST-Ericsson’s office of the CTO].

“Bottom line: The industry is clearly collaborating and targeting wide I/O standards. It’s only a question of timing now.”

Note: If you need to follow 3D IC developments closely or you’re convinced that you need to know more about the topic now, there’s still time to sign up and attend the 3D day at the Electronic Design Process Symposium being held in Monterey, CA on April 7 and 8. Check it out here and sign up here. [But hurry, time grows short!!!]

If you’d like to see the whole wide I/O article from Yole Développement , you’ll find it here.

About sleibson2

EDA360 Evangelist and Marketing Director at Cadence Design Systems (blog at https://eda360insider.wordpress.com/)
This entry was posted in EDA360, Low Power, Packaging, Silicon Realization. Bookmark the permalink.

5 Responses to More on wide I/O and 3D ICs: It’s coming. Are you ready? Need to buy a clue?

  1. Personally I don’t have much faith in wide I/O, it seems like you are just multiplying the number of points where failure will take down your system. Multiple serial links with redundancy seem like a better idea to me.

    • sleibson2 says:

      I think you’ve got to look at what we’re already using. Take a look at a high-end PC motherboard with three channels of DDR3 running from the processor or memory controller to three DDR3 DIMMs. That’s three quarters of a Wide I/O connection but done with pc-board geometries, multiple pc boards (motherboard plus three DDR3 DIMM boards at a minimum) plus the processor/memory controller IC socket and the DIMM sockets. We make that work. I think we’ll make 3D assembly of Wide I/O chips work too, but not without some solid maunfacturing engineering.

  2. Stephan says:

    Kevin,

    the point about WideIO (if I’m not mistaken) is the increasing speed of the serial link, which gets more difficult to route on the board and also power consumption significatly increases. See …
    “The key reason driving wide I/O interfaces is
    lowering the device power while maintaining the
    same performance and bandwidth requirements. In
    some cases you can reduce the power from 10W
    to 4W,” says Calvin Cheung, vice president of
    engineering for application and design at Taiwanbased
    packaging and testing house Advanced
    Semiconductor Engineering (ASE).

    Cheers
    Stephan

    • sleibson2 says:

      Actually, there are pros and cons for both parallel and serial I/O. Serial links need to run faster, but use low-voltage differential signaling so the power doesn’t need to be that great. But the serialization/deserialization adds latency to the connection, which can be a problem for latency-sensitive applications. Wide I/O recognizes that the rules change when you go to 3D packaging. Suddenly, 1000+ connections to a memory chip aren’t ridiculously out of the question. In fact, they can be practical when silicon die are bonded together in a 3D package. Xilinx is making a similar sort of engineering decision by using 2.5D assembly that employs interposers made with 65nm design rules to stitch together several Virtex 7 tiles to make a big FPGA.

  3. On DDR3: most other buses on a PC have gone serial. You could argue that you get lower latency on a parallel bus like DDR3, but since it does block transfers rather than individual memory locations that’s probably not true, and the energy efficiency is probably low too. With multiple memory chips and multiple processors the best communication architecture would be something where you have direct connections between any given CPU and the memory it’s using which doesn’t contend with other CPUs, that would probably be some kind of packet-switched network. The DDR approach is still in use because there’s a shared cache, i.e. the requirement for coherent shared memory (SMP) is what justifies using it, but SMP doesn’t scale.

    Also, the more components in a system the more likely it is to have broken parts. An IBM engineer at a presentation last year said we are getting the point where large die will be known “mostly good” rather than “good” coming out of test, and the numerous 3D-IC talks I have been to tend to indicate that TSV technology s not particularly reliable at this point. So design needs to move to using failure tolerant techniques so that the functional yield of IC processing and packaging stays high.

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