Herb Reiter on the 3D landscape as he sees it today

Herb Reiter is the industry’s cheerleader for 3D assembly. He’s the president of his own company, EDA2 ASIC, and he’s a 3D consultant to the Global Semiconductor Alliance. Reiter has been trying to pull the industry into 3D mode for three years now. He spoke at last week’s Electronic Design Processes Symposium in Monterey and the following is a summary of his remarks:

We need to work much closer as an industry when working with 3D design because we’re putting an entire system together. We also need to learn to comply even more than today with certain standards. Moving from 2D design to 3D is like moving from a 50-acre ranch to a condo in the city. You don’t have as much flexibility in a condo living with other people in the building as you do on your own 50-acre parcel but you can create living space for a lot more people with a lot less real estate.

2D environments have been common for a while now, either as multiple chips on a 2D circuit board (since the 1960s) or as a 2D SoC (since 1995). The big challenge we face in the 2D SoC design space is heterogeneous integration: combining processors, memory, analog, and RF on one piece of silicon is expensive because it’s not very efficient. For example, it’s far more efficient to build memory using a memory-IC process technology than it is to implement memory using an IC process that’s optimized for logic. Analog and RF structures are even less efficient in this regard with respect to area usage or circuit quality.

3D assembly isn’t new—it has been around for many, many years. People have been mounting packages on top of packages since the early DRAM days of the 1970s when memory vendors stacked two 16-kbit memory DIPs and soldered them together to create a 32-kbit device. This was a popular solution to memory expansion in the early 8-bit microcomputers of the 1970s such as the Radio Shack TRS-80 and the Dick Smith System 80 from Australia. You get some space efficiency with this package-on-package approach but you don’t get a performance boost and the resulting package height isn’t very desirable, especially for volume-constrained applications such as mobile devices.

System-in-package design has also been around for a while. People have been wire-bonding such systems for many years now and this sort of design is common in mobile-phone handset designs. However, the pin-count is limited. If you need to bond out 1000 pins, you’ll face major challenges.

What’s happening today in 3D is 2.5D and full 3D solutions. The 2.5D solutions use a silicon or glass interposer to mount active die side by side. The advantage here is that you get high-density interconnect between the chips mounted to the interposer. Xilinx has announced plans to use this approach to create large, tiled versions of its Virtex 7 FPGAs. (See “Need really big FPGAs? Xilinx will be taking the “3D” route for initial Virtex 7 parts“.)

Full 3D assembly stacks die on top of each other and the chip-to-chip interconnections run through the die using through-silicon vias (TSVs). This approach gives system designers all the benefits they’re looking for in terms of compact volume, higher performance, and lower power (because the need for high-power I/O drivers—which consume 20-40% of a chip’s power—is significantly reduced for chip-to-chip communications in a 3D stack).

However, let’s be honest. Full 3D assembly is not a production technology today (with one exception) although many companies have pilot programs to experiment with the technology. That one exception is in your pocket if you own a smartphone. Most if not all smartphone cameras use some sort of true 3D assembly with TSVs. However, these cameras use much larger, much thicker TSVs than desired for 3D stacking of digital, analog, and RF chips.

Over the past two or three decades, the chip-manufacturing, IC-packaging, and board-assembly processes have become increasingly separated. As a result, the types of design and assembly we want to accomplish with 3D are made more difficult because they cross the corporate boundaries within this ecosystem. The current terrain isn’t going to work for us in a 3D world.

One very interesting aspect of the move to 3D is in the realm of system architecture. 3D assembly forces you to entirely rethink system architecture because you can do a lot of things in a 3D assembly that you cannot do on a printed-circuit board. System architects in particular become very excited when they’re first exposed to 3D concepts because they immediately see new possibilities for architectural innovation with 3D packaging.

Wide I/O memory is just one such example of architectural change. If using conventional packaging on circuit boards, the 1000+ pins needed for Wide I/O memory is simply not feasible from a technology or from a cost perspective. Yet it’s quite possible in the 3D realm and Wide I/O memory delivers more memory bandwidth with lower power consumption at the same time. These combined qualities promise a real revolution in system architecture.

In fact, moving memory off of the logic die and onto separate, 3D-attached memory die(s) is far more cost effective because you can build the memory using a memory-optimized IC process that puts more memory in the same amount of silicon and because you can stack memories so that neither the logic die nor the memory dies get too large or too expensive to produce.

IP reuse is yet another 3D advantage. You can basically use an existing standard part (die), strip off the I/O buffers if possible, and use the resulting hard IP block as a known entity in a 3D chip design. You can use what’s proven, in a proven process technology, and add it to a new design. This approach has time-to-market advantages, reduces risk, and cuts NRE.

If you take a look at an Apple iPhone3 circuit board, you’ll see a large IC that’s the Apple A4 processor, which is a system-in-package design with a processor chip and two DRAM memory chips. You’ll also see two more large Flash memory chips on the board. These three chips alone take up a lot of real estate. With 3D assembly, there would be a substantial reduction in pc-board area, which would allow the phone’s size to be reduced or would allow more features to be added.

About sleibson2

EDA360 Evangelist and Marketing Director at Cadence Design Systems (blog at https://eda360insider.wordpress.com/)
This entry was posted in 3D, Packaging, System Realization. Bookmark the permalink.

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