Memory to processors: “Without me, you’re nothing.” DDR4 is on the way.

We talk endlessly about multi-processor SoCs (MPSoCs) but give little attention to memory. Memory is a given. Really? Not, not really. Today’s processor cores have a voracious appetite for memory. They need plenty of memory to shovel instructions into the open maws of the processors’ execution units the way stokers had to shovel coal into the furnaces that powered the Titanic’s steam engines. They need memory to hold the large data sets we now deal with routinely (audio, images, and video). In short, MPSoCs need memory with lots of capacity and lots of bandwidth. Memory architecture, as much as processor architecture, can make or break an SoC design.

That’s why today’s announcement of DDR4 controller, PHY, and verification by Cadence is important. DDR4 SDRAM is the next step on the evolutionary ladder for external SDRAM DIMMs. Although JEDEC hasn’t released the final specification yet, two of the top three DRAM vendors, Samsung and Hynix, have already introduced memory modules based on the DDR4 specification, as it stands today.

Truthfully, we’re just entering the phase where DDR3 memories are becoming the leading mainstream SDRAMs, finally displacing DDR2 SDRAMs. Like previous versions of DDR, you can expect DDR2 memories to begin their long slow fade to oblivion. They’ll be around-surely—for years, but new designs trend to DDR3 for lower power and greater memory bandwidth. Be assured, the same will happen with DDR4, which features lower power requirements than DDR3 (due to a lower operating voltage) and greater bandwidth. However, that displacement won’t happen for years. Don’t even expect to see volume production of DDR4 memories until 2012 and don’t expect to see DDR4 gain significant traction until 2013—assuming you believe the pundits. It might be even later.

So why would Cadence bother to introduce DDR4 controller, PHY, and verification IP so early? Even before the JEDEC standard is released? That’s easy. There are certain leading-edge IC and system vendors that need to be ready with chips and systems as soon as possible. Designers at those vendors need that DDR4 IP now to begin their design cycles. That’s the only way to catch the wave.

Cowabunga!

About sleibson2

EDA360 Evangelist and Marketing Director at Cadence Design Systems (blog at https://eda360insider.wordpress.com/)
This entry was posted in EDA360, IP, Low Power, SoC Realization, System Realization. Bookmark the permalink.

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