Last November, I wrote a blog entry about Xilinx’ plan to use 2.5D assembly techniques to create large Virtex 7 FPGAs using tiled 28nm silicon with interposers. (See “Need really big FPGAs? Xilinx will be taking the “3D” route for initial Virtex 7 parts.”) Now, Xilinx has published more details in the cover story of the company’s 1Q 2011 issue of Xcell Journal, written by Xcell Journal’s publisher Mike Santarini. The article is titled “Stacked & Loaded: Xilinx SSI, 28-Gbps I/O Yield Amazing FPGAs.”
The first thing to note is the assembly of the 2.5D SSI product (see Figure 1 below). The device uses a passive silicon interposer manufactured with 65nm design rules—with through-silicon vias (TSVs) but no active devices on the silicon—as a circuit board for the 28nm silicon FPGA slices or tiles. The silicon interposer provides high-density interconnect between the FPGA slices and also serves as a dimensional translator between the 28nm FPGA slices with their fine-pitched microbumps and the package substrate with conventional C4 solder bumps (IBM developed the C4 process in the 1960s).
Figure 1: Xilinx 2.5D assembly technique allows the company to create large FPGAs with 28nm slices. (Image courtesy of Xilinx.)
Xilinx calls this assembly “SSI” (stacked system interconnect) and this approach to large-FPGA assembly provides two big benefits according to Liam Madden, the Xilinx corporate VP of FPGA development and silicon technology. “We can get many more connections within the silicon than you can with a system-in-package. [There are “more than 10,000 routing connections between FPGA slices.] But the biggest advantage of this approach is power savings. Because we are using chip interconnect to connect the dice, it is much more economical in power than connecting dice through big traces, through packages or through circuit boards,” says Madden in the Xcell Journal article.
Madden continues: “One of the beautiful aspects of this architecture is that we were able to establish the edges of each slice [individual die in the device] along natural partitions where we would have traditionally run long wires had these structures been in our monolithic FPGA architecture. This meant that we didn’t have to do anything radical in the tools to support the devices. As a result customers don’t have to make any major adjustments to their design methods or flows.”
This is an important aspect of 2.5D use that should not be overlooked. The fact that Xilinx is using 2.5D packaging doesn’t impact the end users’ behavior and doesn’t force them to use new FPGA development tools. The 2.5D aspect of the new Virtex 7 FPGAs is effectively invisible, which is precisely how customers prefer to deal with such new technologies. Making the packaging advances invisible will aid acceptance.
Finally, to show how real this 2.5D stuff is, here’s a cross-section microphotograph of an assembled device:
Figure 2: Microphotograph of an assembled Xilinx Virtex 7 SSI device. (Image courtesy of Xilinx.)