3D Thursday: More on the Xilinx Virtex 7 with 2.5D tiling. Wave of the future or stopgap measure?

Last November, I wrote a blog entry about Xilinx’ plan to use 2.5D assembly techniques to create large Virtex 7 FPGAs using tiled 28nm silicon with interposers. (See “Need really big FPGAs? Xilinx will be taking the “3D” route for initial Virtex 7 parts.”) Now, Xilinx has published more details in the cover story of the company’s 1Q 2011 issue of Xcell Journal, written by Xcell Journal’s publisher Mike Santarini. The article is titled “Stacked & Loaded: Xilinx SSI, 28-Gbps I/O Yield Amazing FPGAs.”

The first thing to note is the assembly of the 2.5D SSI product (see Figure 1 below). The device uses a passive silicon interposer manufactured with 65nm design rules—with through-silicon vias (TSVs) but no active devices on the silicon—as a circuit board for the 28nm silicon FPGA slices or tiles. The silicon interposer provides high-density interconnect between the FPGA slices and also serves as a dimensional translator between the 28nm FPGA slices with their fine-pitched microbumps and the package substrate with conventional C4 solder bumps (IBM developed the C4 process  in the 1960s).


Figure 1: Xilinx 2.5D assembly technique allows the company to create large FPGAs with 28nm slices. (Image courtesy of Xilinx.)

Xilinx calls this assembly “SSI” (stacked system interconnect) and this approach to large-FPGA assembly provides two big benefits according to Liam Madden, the Xilinx corporate VP of FPGA development and silicon technology. “We can get many more connections within the silicon than you can with a system-in-package. [There are “more than 10,000 routing connections between FPGA slices.] But the biggest advantage of this approach is power savings. Because we are using chip interconnect to connect the dice, it is much more economical in power than connecting dice through big traces, through packages or through circuit boards,” says Madden in the Xcell Journal article.

Madden continues: “One of the beautiful aspects of this architecture is that we were able to establish the edges of each slice [individual die in the device] along natural partitions where we would have traditionally run long wires had these structures been in our monolithic FPGA architecture. This meant that we didn’t have to do anything radical in the tools to support the devices. As a result customers don’t have to make any major adjustments to their design methods or flows.”

This is an important aspect of 2.5D use that should not be overlooked. The fact that Xilinx is using 2.5D packaging doesn’t impact the end users’ behavior and doesn’t force them to use new FPGA development tools. The 2.5D aspect of the new Virtex 7 FPGAs is effectively invisible, which is precisely how customers prefer to deal with such new technologies. Making the packaging advances invisible will aid acceptance.

Finally, to show how real this 2.5D stuff is, here’s a cross-section microphotograph of an assembled device:

Figure 2: Microphotograph of an assembled Xilinx Virtex 7 SSI device. (Image courtesy of Xilinx.)

About sleibson2

EDA360 Evangelist and Marketing Director at Cadence Design Systems (blog at https://eda360insider.wordpress.com/)
This entry was posted in 3D, EDA360, Silicon Realization and tagged , , , . Bookmark the permalink.

6 Responses to 3D Thursday: More on the Xilinx Virtex 7 with 2.5D tiling. Wave of the future or stopgap measure?

  1. Dean Stevens says:

    It’s an interesting approach, but they would have been better served to be more modular in their approach to defining the tiles. It seems more like a stopgap to me. It’s another step in the road to true monolithic 3d IC’s…

  2. sleibson2 says:

    Dean, multiple chips is always a stopgap, or pur another way, it’s always a way to stretch current monolithic capability into a capacity not reachable by current monolithic economics. Most famous case in point: Intel’s Pentium Pro, which was a laughingstock when introduced because it paired a processor with a fast SRAM cache chip in one two-cavity package. But the Pentium Pro achitecture could be done as a monolithic chip by the next process generation and the architecture led to a tremendous golden age for the Pentium architecture. However, multichip packaging is older than that. It was common practice in the 1970s to mount one 16K DRAM DIP on top of another (early chip stacking with double packaging). Mostek used a 2-cavity design to accomplish the same thing: make packaged DRAMs that had more capacity than monolithic chipmaking could achieve at the time. What’s old is new again.

  3. Dean Stevens says:

    Hi Steve- All true. At some point, though, it won’t be economical to continue to scale down feature sizes in order to integrate more functionality on a single die. That’s when (I hope) we’ll start to see the term “monolithic” truly extended into the third dimension.

  4. sleibson2 says:

    Hi Dean, I think there’s a real race on. I agree with you that there’s a point coming where things won’t scale. Wally Rhines’ data shows that at 20nm, the cost per gate will cease to fall and will actually start to rise due to double patterning. We will either figure a way to solve that engineering economic problem or we will take a divergent path either through on-die 3D or by adopting a different (not CMOS) monolithic process technology entirely. We’ve seen this many times in the past. In the late 1950s, the US military had electronics companies working on micromodules for miniaturization when what we really needed (and got) was integrated circuits. In the 1970s, we “knew” that NMOS was going to be king of the IC process technologies because CMOS was slow and needed more area. In the 1980s, we “knew” that GaAs would supplant CMOS when it ran out of steam at a few tens of MHz. At any given time, we “know” a lot of things that don’t turn out to be true. I wish my crystal ball was less cloudy. I could make a killing.

  5. Dean Stevens says:

    Hi Steve- Yeah, but the inflection points are always the most exciting. A functioning crystal ball would take all of the fun out of it…

  6. Gregg Pulley says:

    Stopgap -vs- future of packaging? A little of both I think. But it’s also a blast form the past.

    The ideas behind this technology are nothing new, not by a long shot. The primary innovation here is scale and achieving the implementation completely within modern Si processes.

    The best and probably most commercially successful example of the MCM comes from IBM circa 1987. The S/370 model 308x processor complex (IBM quit using the term CPU after losing a legal battle with Amdahl) were implemented using Thermal Conduction Modules (TCM). Each consisted of an 12×12 array of ECL flip-chips bonded to a 33 layer ceramic micro interconnect within a single water cooled module. Dick Chu was the brain child behind the TCM and is still considered a foremost expert in art of thermal and high density package design.
    http://books.google.com/books?id=c2YxCCaM9RIC&pg=PA48&lpg=PA48&dq=IBM+thermal+conduction+module+TCM&source=bl&ots=0fECnsp0fd&sig=BCCwKPaBtD61jA9vdDO_UIgTIGw&hl=en&ei=gvO9TeqONoyctwfah5HHBQ&sa=X&oi=book_result&ct=result&resnum=10&ved=0CGcQ6AEwCQ#v=onepage&q=IBM%20thermal%20conduction%20module%20TCM&f=false

Leave a Reply

Fill in your details below or click an icon to log in:

WordPress.com Logo

You are commenting using your WordPress.com account. Log Out / Change )

Twitter picture

You are commenting using your Twitter account. Log Out / Change )

Facebook photo

You are commenting using your Facebook account. Log Out / Change )

Google+ photo

You are commenting using your Google+ account. Log Out / Change )

Connecting to %s