Even more 3D Thursday: Ed Lee talks to Qualcomm’s Riko Radojcic about 3D EDA standards

It seems today’s inbox is chock full of 3D talk. Here’s the third blog entry today about 3D. It’s a pointer to Ed Lee’s conversation with Qualcomm’s Director of Engineering Riko Radojcic about 3D and EDA standards. You’ll find many tidbits in this discussion including Si2’s growing involvement with 3D standards, which I coincidentally discussed with Si2’s president Steve Schulz just yesterday. Click here for Ed Lee’s interview with Riko Radojcic on EDACafe.


About sleibson2

EDA360 Evangelist and Marketing Director at Cadence Design Systems (blog at https://eda360insider.wordpress.com/)
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3 Responses to Even more 3D Thursday: Ed Lee talks to Qualcomm’s Riko Radojcic about 3D EDA standards

  1. Dean Stevens says:

    I can’t help but wonder whether the tools required to design the truly integrated “future” 3D systems will come from the big EDA vendors, or from not-yet-well-known startups. History suggests that a lot of the innovation and early risk taking in EDA really falls to startups that may get eaten by the “big fish.” Right now, I’m seeing a lot of work on these tools happening in university labs, internal CAD teams and companies like ours that are trying to push the boundaries of the technology.

  2. sleibson2 says:

    Hi Dean, thanks for leaving a comment. I’ve had many conversations about this topic with several experts inside of Cadence and in the community, such as Herb Reiter who I think of as “Mr. 3D.” The overwhelming sentiment is that EDA is not the long pole in the tent here. As far as creating the proper alignment among stacked chips and interposers, the design tools are there (at least the ones I know about at Cadence). What’s not there is the modeling of stress fracturing caused by TSVs, which is because we don’t yet have the analytical data needed to create the models to put into the EDA tools. What’s also not there is some sort of automatic partitioning mechanism for spreading functions across dies. However, the gross partitioning algorithms we currently use–logic, memory, analog, RF–that align with the process technologies for each die, that back-of-the-envelope partitioning will carry us pretty far into the future and may end up being the way it will always be done. For now, that’s the way it will be done because that’s the most efficient way to use the various silicon IC process technologies. Once we transition to graphene or whatever’s next, then all bets are off.

  3. Dean Stevens says:

    Hi Steve- Thanks for the follow-up. I agree completely with your assessment of the current state of the tool flow for TSV based vertical integration. My intent with my previous comment was to try to start some discussion about the tools for the next wave, which Mr. Radojcic refers to as “Some future 3D implementations – like stacking logic on logic – does require disruptive change in design tools.” When we move into the realm that my group is working in, true monolithic 3D ICs, your comment “all bets are off” applies perfectly.

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