On Friday, Altera posted a video that shows the company characterizing some of the features of the upcoming Stratix V FPGA, being built with a 28nm process technology. The largest member of the Stratix V FPGA family will incorporate nearly 4 billion transistors on one die, which are used to construct one million on-chip logic elements and various hard-IP logic blocks. The Stratix V FPGA family will also have 28Gbps serial transceivers, although this video shows transceivers operating at “only” 14.1Gbps.
–
See Loring Wirbel’s EDN coverage of the Altera Stratix V announcement from April 19 here: http://www.edn.com/blog/FPGA_Gurus/34740-Stratix_Strategy_for_Fifth_Generation.php
EDA360 Insider 