Friday video (late bonus): Altera demos some features from 28nm Stratix V FPGA

On Friday, Altera posted a video that shows the company characterizing some of the features of the upcoming Stratix V FPGA, being built with a 28nm process technology. The largest member of the Stratix V FPGA family will incorporate nearly 4 billion transistors on one die, which are used to construct one million on-chip logic elements and various hard-IP logic blocks. The Stratix V FPGA family will also have 28Gbps serial transceivers, although this video shows transceivers operating at “only” 14.1Gbps.

See Loring Wirbel’s EDN coverage of the Altera Stratix V announcement from April 19 here:

About sleibson2

EDA360 Evangelist and Marketing Director at Cadence Design Systems (blog at
This entry was posted in EDA360, IP, Silicon Realization and tagged , , . Bookmark the permalink.

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