EDA360: One year later

Today is the first anniversary of the day Cadence published the EDA360 vision paper. Quite a lot has happened in that year. There have been many changes inside of Cadence and throughout the industry. Here are just a few:

APRIL 2010

  • Cadence debuts the Palladium XP verification computing platform, a key element used for System Realization

MAY 2010

  • Cadence acquires leading EDA and IP vendor, Denali Software.

JUNE 2010

  • Cadence announces support for TSMC Analog/Mixed-Signal (AMS) Reference Flow 1.0 for advanced 28-nanometer process technology.
  • Cadence adds TLM-driven design and verification, 3D-IC design and integrated DFM capabilities to TSMC Reference Flow 11.0
  • Comprehensive open-source reference flow for SoC verification using the UVM standard announced.

JULY 2010

  • Cadence and ARM collaborate to create ARM-optimized System Realization


  • Cadence reorganizes R&D and marketing functions around the three Realizations in the EDA360 vision: System Realization, SoC Realization, and Silicon Realization.


  • SMIC, Mainland China’s most advanced silicon foundry, adopts the Cadence Silicon Realization product line for advanced node, low-power designs.
  • Cadence begins to provide customers with an optimized implementation methodology for the new ARM Cortex-A15 MP Core processor.


  • Open-Silicon announces that it has successfully taped out a high-performance 2.4GHz processor using the Cadence Silicon Realization product line.


  • Fujitsu Semiconductor Limited begins supporting the Cadence C-to-Silicon Compiler for high-level synthesis in ASIC design flows.
  • SMIC adopts Cadence DFM and low-power Silicon Realization for its 65nm reference flow.
  • Electronic Design magazine names the Cadence Encounter Digital Implementation System 9.1 one of the best EDA technology offerings in 2010.
  • Cadence Virtuoso Accelerated Parallel Simulator wins the Elektra Electronics Industry Awards 2010 as the best design tool and development software.


  • Cadence announces a reference flow for the Common Platform 32/28-nanometer technology.
  • Cadence announces a digital end-to-end flow at 28nm.
  • Cadence teams with STARC, a Japanese design consortium, to create a Cadence-based 32/28-nanometer for DFM flow
  • Spreadtrum Communications announces successful tape out of its first 40nm, low-power chip using the Cadence Silicon Realization flow.


  • IMS CHIPS announces adoption of Cadence Silicon Realization technologies for its special mixed-signal gate-array technology.
  • Broadcom Corporation announces expanded use of the Cadence Verification Computing Platform, Palladium XP, to help validate its complex system designs before committing them to silicon.

MARCH 2011

  • Cadence announces major enhancements to the Virtuoso-based custom/analog flow to boost productivity across the entire Silicon Realization flow from initial design specification to final GDSII and for process nodes down to 20nm.
  • Cadence announces the industry’s first wide I/O memory controller IP solution, essential for 3D IC design.

APRIL 2011

  • Cadence announces a comprehensive DDR4 design solution that includes controller and PHY design IP, verification IP, and memory models that will allow SoC designers to start creating SOCs using the emerging DDR4 SDRAM memory standard.

About sleibson2

EDA360 Evangelist and Marketing Director at Cadence Design Systems (blog at https://eda360insider.wordpress.com/)
This entry was posted in EDA360, Silicon Realization, SoC Realization, System Realization. Bookmark the permalink.

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