A recent article about System Realization published on the Design and Reuse site caught my eye because it has some insightful things to say about using high-level modeling to develop complex new systems. The article is by Luca Fossati of the European Space Agency and is titled “TLM 2.0 Standard into Action: Designing Efficient Processor Simulators.” Here are some of the key insights from Fossati’s article:
“The design of … complex embedded systems is a difficult problem, requiring designers with skills and experience to identify the best solution. In this context, the ability to accurately, quickly, and easily predict properties of computer systems is useful for computer architects, designers, and software developers. Because simulators are not subject to the same constraints as their physical counterpart, they are easier to create, modify, and observe. Among such hardware simulators, the so called Virtual Platforms (VPs) are gaining more and more attention. They combine high-speed micro-processor simulators and functional C/C++ models of the remaining system’s building blocks, to provide a highlevel model of the hardware to the software developer and, in the preliminary development stages, to the system architect.”
So are systems running C, C++, and assembly code the right sort of things to target? What about all of those other much-hyped embedded programming languages? There’s one answer in a recent blog by EDN’s Paul Rako, who writes about the recent results of the UBM 2011 Embedded Market Study. Although the study sell for a few dollars, some of the results are public including this graph of embedded programming language usage:
It would seem that these kinds of virtual prototyping systems are indeed targeting the right embedded languages.
“In order to enable effective Virtual Platform design there is the need for hardware description languages which are both expressive, fast, and which enable targeting detailed low level hardware structures as well as system-level models. In particular SystemC has grown more and more popular; this language fuses a well-known syntax with powerful constructs, enabling the modeling and simulation of complex systems. SystemC consists of a set of C++ libraries devoted to building system-level executable models of mixed hardware-software systems at several levels of abstraction; many constructs are provided, among which modules, channels, and interfaces. The true advantage of SystemC as a specification language lies in the fact that it encompasses all the important hardware modeling features, as well as providing powerful modeling constructs for system level design. This ensures that the transition to a SystemCbased methodology entails no compromise in terms of expressive power at the lower levels of abstraction, and yet it forms a useful framework for modeling at the higher levels.
… The underlying concept of TLM is to model only the level of detail that is needed, hence both boosting simulation speed and improving design flexibility, as changes to the design are also relatively easy and cost effective, not having yet delved in low-level details.”
Last week at the Embedded Systems Conference in San Jose, Cadence introduced the System Development Suite, which includes the Virtual System Platform, a virtual prototyping tool that’s very much like what Fossati writes about in his article. The Virtual System Platform works with a library of TLM IP models. These models are provided as SystemC source code so they can be modified as needed for adapting to new design requirements or tuned for specific performance needs. Fast processor models provide the high-performance execution speed required for an effective software-development solution. The Cadence VirtualSystem Platform supports ARM Fast Models and Imperas fast processor models that can execute hundreds of millions of software instructions per second (MIPS). These models support lock-step software and multiprocessor hardware debugging through a unified developer cockpit.
There’s more detail in Fossati’s article, which you’ll find here.