3D Thursday: Intel and FinFETs (Tri-Gate transistors)—a different kind of 3D

Earlier this month, Intel announced that it will be using Tri-Gate transistors (FinFETs) to build microprocessors at the 22nm process node. The microprocessor is code-named “Ivy Bridge.” It will be a 22nm version of the company’s Sandy Bridge processor and will be the first high-volume chip to use such “3D” transistors. Intel is calling this FET structure the “Tri-Gate” transistor because the gate wraps three-quarters of the way around an elevated gate. Others have called this structure a FinFET for several years, but FinFETs haven’t gone into production before this.

Although every planar transistor made in the last 50 years (bipolar or DET) has been “3D” in the sense that diffusions reach down into the silicon (and always have) and the gate oxide and poly or metal gate and interconnect have always risen above the top plane of the silicon, not to mention trench capacitors, TSVs, and other such 3D structures. Usually, the term “3D” is reserved for structures with multiple vertical layers of active devices but FinFETs and Intel’s Tri-Gate transistors are perhaps “more 3D” than the 50 years worth of planar transistors that have come before because the FET channel itself now rises above the wafer’s top plane in these devices.

Here’s an illustration (courtesy of Intel) of a conventional FET (on the left) and a Tri-Gate transistor (on the right):

Note that both transistors are really 3D structures but the gate of the Intel Tri-Gate transistor wraps around three sides of the transistor’s elevated channel.

Why complicate the transistor fabrication process at 22nm to make a wraparound gate? Because, says Intel, Tri-Gate transistors can operate at lower Vdd, which in turn can reduce operating power by 50% and can increase performance by 37% (compared to 32nm planar transistors) while increasing wafer cost by 2% to 3%.

It shouldn’t surprise you that everyone isn’t sold on FinFETs just yet. According to this article on the Xbit Labs site, TSMC won’t be going to FinFETs at the 20nm node. “We need the ecosystem to be ready for FinFETs, which means design tools, IP, design kits and so on. For us, 20nm will be planar,” said Maria Marced, president of TSMC Europe in this EETimes article.

For another take on the Intel Tri-Gate transistor announcement, see David Lammers’ article “Experts: Intel’s Tri-gate Not Easy to Match” over on the Semiconductor Manufacturing & Design Community site.

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About sleibson2

EDA360 Evangelist and Marketing Director at Cadence Design Systems (blog at https://eda360insider.wordpress.com/)
This entry was posted in 3D, EDA360, Low Power, Silicon Realization, SoC Realization and tagged , , , , , , . Bookmark the permalink.

3 Responses to 3D Thursday: Intel and FinFETs (Tri-Gate transistors)—a different kind of 3D

  1. Interesting to note that in his keynote at CDNLive EMEA on May 3, STMicro’s Philippe Magarshack also spoke of FinFETs as being the next major step on their roadmap — i.e. like Intel, STMicro appears to be “sold” on FinFETs. Additionally, I came away with the impression that ST believes the FinFET structure will help keep silicon useful get down to 15 nm (vs. switching to more exotic things like carbon nanotubes, etc.)

    (FWIW, my blog on the event also captures Magarshack’s related remarks on low poer design:
    http://www.cadence.com/Community/blogs/fv/archive/2011/05/10/2011-cdnlive-emea-highlights-amp-image-gallery-an-eda360-spring-festival-of-deliverables.aspx?postID=1275878

  2. MIT says:

    Intel is not alone Amd made a press release and here is the link

    http://www.amd.com/us/press-releases/Pages/Press_Release_42454.aspx

    Sunnyvale, CA — 9/10/2002 — SUNNYVALE, CA—September 10, 2002—AMD (NYSE: AMD) today announced it has fabricated the smallest double-gate transistors reported to date using industry standard technology. These transistors, measuring ten nanometers, or ten billionths of a meter in length (gate), are six times smaller than the smallest transistors currently in production. AMD’s research breakthrough could foster the placement of a billion transistors on the same size chip that currently holds 100 million transistors, enabling a vastly richer computing experience.

    Transistors are the miniscule on/off switches that make up the integrated circuits in today’s microprocessors. A double-gate transistor structure effectively doubles the electrical current that can be sent through a given transistor. The Fin Field Effect Transistor (FinFET) design relies upon a thin vertical silicon “fin” to help control leakage of current through the transistor when it is in the “off” stage. This design combination allows for the creation of new chips with enhanced performance and ever-shrinking geometries.

    “Transistor development is essential to the creation of higher-performing products for our customers,” said Craig Sander, AMD’s vice president of Technology Development. “The entire semiconductor industry is working to meet the increasing challenges of developing new transistor designs that are smaller and higher-performing and yet can be manufactured with minimal deviation from today’s industry standard manufacturing processes. The FinFET transistor indicates we can continue to deliver very high performance products while preserving the basic technology infrastructure our industry relies upon.” …….

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