ARM suggests you take the “M” train for your next ASIC or SoC using the company’s new Cortex-M System Design Kit

Last week, ARM introduced a System Design Kit to facilitate the incorporation of the company’s 32-bit Cortex-M processors in ASICs and SoCs. Called the ARM Cortex-M System Design Kit (CMSDK), the package includes:

  • Example systems for ARM Cortex-M0, Cortex-M3 and Cortex-M4 processors
  • Example peripherals to aid migration of existing components from 8-bit or 16-bit systems
  • AMBA AHB and APB components, including GPIO, timers, watchdog, and UART
  • Compilation and simulation scripts for the Verilog environment
  • Software drivers and example test code based on CMSIS (Cortex Microcontroller Software Interface Standard) for easy software reuse
  • Project files for ARM RVDS, Keil MDK, and GNU compilers.

What’s different about the ARM Cortex-M series of 32-bit RISC processor cores? They’re small. According to Tom Halfhill’s Microprocessor Report article on the Cortex-M series (March 2, 2009, subscription required), an ARM Cortex-M0 processor requires only about 12K gates to implements and an ARM Cortex-M3 requires 33 to 60K gates. These processors exclusively use the 16-bit ARM Thumb instructions set. Compare these numbers to the older, less capable ARM7TDMI processor core, which has been a mainstay processor core for ASIC designers and SoC Realization teams. The ARM7TDMI-S core requires 48K gates for implementation and delivers less performance than the ARM Cortex-M3 core.

The much smaller ARM Cortex-M0 processor core can run as fast as the ARM7TDMI-S core (in terms of maximum clock rate) and delivers nearly the same performance per MHz while requiring only a quarter of the implementation gates. That’s a big, big difference. What do you lose? Not that much really. A fast multiplier (but you can have a fast one if you’re willing to spend the gates), a hardware divider, any chance for a memory-protection unit on the Cortex-M0 (but optional with the Cortex-M3).

However, you get some bonuses too like a far more complex, nested vectored interrupt controller that handles as many as 32 interrupts for theCortex-M0 core (but only 1 interrupt for the rock-bottom 12K gate cost) and as many as 240 interrupts for the Cortex-M3 core compared to the ARM7TDMI core’s two (count ‘em, 2) external interrupts.

About sleibson2

EDA360 Evangelist and Marketing Director at Cadence Design Systems (blog at https://eda360insider.wordpress.com/)
This entry was posted in ARM, EDA360, SoC Realization and tagged , , , , , . Bookmark the permalink.

Leave a Reply

Fill in your details below or click an icon to log in:

WordPress.com Logo

You are commenting using your WordPress.com account. Log Out / Change )

Twitter picture

You are commenting using your Twitter account. Log Out / Change )

Facebook photo

You are commenting using your Facebook account. Log Out / Change )

Google+ photo

You are commenting using your Google+ account. Log Out / Change )

Connecting to %s