OK. Here’s the deal. Cadence wants you to know about the true bleeding edge in Silicon Realization. The ASIC/SoC silicon frontier’s at 20nm. FYI: 28nm is already a day late and a process node short (thanks Richard G!). Want to find out more about 20nm? There’s a technical panel. On Monday. At DAC. With lunch. You need to register.
But first, here’s the critical info:
When: Monday, June 6, 11:30 AM – 1:30 PM
Where: Omni Hotel Grand Ballroom Salon D (Level 4). That’s next to the San Diego Convention Center
What: Design and implementation at 20nm is uncovering unprecedented challenges that are shaking the very core of electronic design. Integrating baseband into the software-configurable, multi-core, application processor of tomorrow, while worrying about how new devices will change the way that we design and address power from architecture to silicon in a memory/bandwidth-enabling 3D-IC, is but one reality that we have to address today. This panel brings together IP providers, semiconductor companies, and EDA vendors to discuss the challenges and approaches that need to be considered when designing and implementing at the 20nm node.
Moderator: Jim Handy, Objective Analysis
Panelists:
- Chi-Ping Hsu – Cadence, Senior Vice President, Silicon Realization
- Simon Segars – ARM, Executive Vice President and General Manager, Physical IP
- Ana Hunter – Samsung, Vice President, Foundry Services
- Philippe Magarshack – STMicroelectronics, Vice President for Design Automation and Libraries, Central Research and Development Group
These are real people discussing real results. No marketing fluff. Not on the panel anyway. I’ll probably be in the audience (adding my fluff quotient to the event).
Register here. Seats are very limited for this extremely special event.
Register now, because you know that free lunch at DAC is like blood in the water to a school of starving piranha.
EDA360 Insider 