On Wednesday at DAC’s show-floor Pavilion, Low-Power Engineering’s Editorial Director Ed Sperling chaired a panel with the intent of giving the industry a report card on its low-power engineering efforts. Along with Sperling on the Pavilion platform were Andrew Brotman, VP of Design Infrastructure at Globalfoundries; Ruggero Castagnetti, a Distinguished Engineer at LSI Corp; and Ambrose Low, Director of Engineering at Broadcom. With the diverse experiences of this panel, DAC attendees got a pretty good cross section of views on low-power SoC design from some pretty experienced eyes.
The panelists wasted no time in pointing the way. “The most significant [power] gains are at the system level” said Brotman.
“As long as I am doubling transistor density at each new process node, power goes up. You can’t get enough gains from the circuit level” said Castagnetti.
Low agreed. “Lower-leakage transistors have high Vt, which prevent you from dropping operating voltage and operating power, so you can’t use them” he said.
Sperling then asked what was working. “Power islands are becoming popular” said Castagnetti. “They are perhaps the best way to maximize power efficiency.” “However,” said Low, “you have to be careful to make sure there are no diodes connected to the voltage power rails” when you use power islands.
Castagnetti continued: “The big challenge is to understand the [SoC’s] use modes” so that you can decide when to power down the islands. He would like to see the development of EDA tools that analyze an SoC’s operating modes and look for opportunities to shut down the various power islands on the SoC. Brotman quickly agreed: “The tool flows need to be able to predict behavior during shutdown.” Low then pointed out that switching an SoC’s power islands on and off placed extra loads on the SoC’s power-distribution systems and that designers need to pay more attention when designing such systems as a consequence.
Castagnetti then turned the conversation to power-aware IP. You need to make sure that all of the IP you’re mixing and matching in an SoC’s design is in line with your power-management goals. Sometimes, IP can’t tolerate low operating voltages. Memories are an example of one type of power-sensitive IP. Drop the operating voltage low enough and the memories lose their contents. Some IP isn’t at all power aware. Some IP is. Power-aware Ethernet IP is one type of IP that has been made power-aware because the awareness requirement is built into the interface standards. Fore example, there’s a well-specified way to bring the Ethernet PHY up after power-down, he said and then noted that the industry is moving in this direction. Low agreed. “Interface IP should enable ports only when traffic is detected” he said. However, Low thinks we have a long way to go before power-aware IP becomes common.
“No one wants to take risks unless they’re required,” warned Castagnetti in reference to power-aware IP. “This [attitude] retards adoption of more aggressive power-management techniques.” Consequently, we have to more when designing at the system level he said.
Castagnetti then switched the discussion to high-level modeling of power-aware IP. These models “need to have power numbers for various use modes” he said. “Try to understand the worst-case use modes for the IP because you can get surprises with worst-case power use.” Low then said “The tools for power analysis are there but the models still have a long way to go.” Brotman differed on that thought. “The tools are there for power estimation at the lower levels but they are immature [for design] at the chip-top level.”
Sperling then asked each panelist about where the low-hanging fruit could be found with respect to low-power design.
Brotman: Turn off your phone. (That got a laugh from the DAC audience.)
Castagnetti: Stop overdesigning SoCs. Bulletproof design eats power.
Low: Power down blocks. Lower the operating voltage to power islands when the block isn’t needed.