Microprocessor Report publishes extremely interesting comparison of STMicroelectronics SPEAr-1300 and Xilinx Zynq ARM-based, dual core application processors

Last month, STMicroelectronics introduced the latest in its line of SPEAr (Structured Processor Enhanced Architecture) application processors and Microprocessor Report has just published a very interesting article about the new products (paid subscription required). The SPEAr-1300 series is based on two 600MHz ARM Cortex-A9 microprocessor cores (upgraded from the 333MHz ARM9 cores used in the earlier SPEAr parts). Each ARM processor core in the SPEAr-1300 embedded application processor has two 32-kbyte L1 caches and the two processor cores share a 512-kbyte L2 cache. The SPEAr-1300 application processor also includes a number of hard-core IP peripherals including a Gigabit Ethernet port, a PCIe/SATA port, and two USB 2.0 ports. In addition, there are 1.3 million uncommitted ASIC gates that can be configured for specific applications and, in a throwback to the disco days of the 1980s, these ASIC gates are configured as a metal-defined gate array so the wafers can be stockpiled awaiting final metal designs.

STMicro SPEAr-1300 Block Diagram

Because of this configurability, Joseph Byrne’s article on the STMicroelectronics SPEAr-1300 introduction is right on the mark when it compares the new product to the Xilinx Zynq application processors currently experiencing a prolonged rollout cycle. (See “Xilinx Zynq EPPs based on two ARM Cortex-A9s create a new category that fits in among SoCs, FPGAs, and microcontrollers.”)

Like the SPEAr-1300 family, the Zynq parts incorporate two ARM Cortex-A9 processor cores but the Xilinx ARM cores run (or will run) at 800MHz. The additional speed comes from the 28nm process technology Xilinx employs for the Zynq line while STMicroelectronics uses a 55nm process technology for the SPEAr-1300 parts.

Both the STMicroelectronics and Xilinx application processors offer many on-chip peripherals but the two do not offer exactly the same features, so the appropriateness of the match will depend on the application (as usual). Perhaps more interesting is the configurability offered by the two application processor families. The STMicroelectronics SPEAr-1300 series offers 1.3 million mask-programmable ASIC gates, which is about the equivalent capacity of the uncommitted FPGA gates available in the Xilinx Zynq 7020 according to the Microprocessor Report article. However, real metal-programmed ASIC gates consume far less silicon than FPGA gates, which more than counterbalances the more advanced process technology used to fabricate the Zynq parts.

As a result, Bynre’s article estimates that the unit cost for the STMicroelectronics processors will be about half that of the Xilinx parts, not including NRE. Although neither of these parts is going to be really expensive, many embedded applications are cost-sensitive to the penny.

The STMicroelectronics SPEAr-1300 series (and the previously announced Xilinx Zynq parts) are indicative of the type of components that System Realization design teams will be considering in the future. Both of these product lines offer access to advanced IC processing nodes without the need for full ASIC design capabilities but still with some level of hardware configurability, not to mention the massive amount of software configurability made possible by a couple of very capable on-chip, 32-bit ARM microprocessor cores.


About sleibson2

EDA360 Evangelist and Marketing Director at Cadence Design Systems (blog at https://eda360insider.wordpress.com/)
This entry was posted in ARM, EDA360, Silicon Realization, SoC Realization, System Realization and tagged , . Bookmark the permalink.

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