The Lucio Lanza DAC Panel: What EDA Isn’t Doing Right

One of the last Pavilion Panels I attended at DAC in San Diego last week was also one of the most interesting. Longtime EDA investor Lucio Lanza brought together three pretty sharp and experienced people to discuss the topic of “What EDA Isn’t Doing Right.” The four panelists were Behrooz Abdi (EVP at NetLogic Systems), Charles Matar (VP of Engineering at Qualcomm), and Alan Nakamoto (VP of Design Services at PMC-Sierra). Now the panelists weren’t there to indict the EDA industry. All agreed that EDA was doing a lot of things right and the electronics industry benefited greatly from EDA. At the same time, ever-expanding silicon capabilities (thank you Moore’s Law) mean that there are always new horizons to conquer and new hills to climb.

Electronic systems have shrunk from multiple boxes to single-box, single-chip systems said Abdi. In networking, for example, separate router, switch, and security boxes have collapsed into single network server boxes. As a consequence, value has migrated from the collection of boxes into the one chip implementing all of the capabilities. The rest is power supplies, enclosures, and connectors.

At the same time, there are very high capital costs involved with developing these big chips. With hardware and software development, a 40nm chip can cost $100 million to create. And, said Abdi, the hardware/software integration is the really expensive part of development. (A common EDA360 theme, by the way.) These high costs are stifling innovation.

Chip startups are becoming extinct because of these high development costs. There have been none in the past two or three years, said Abdi, who concluded that the EDA industry needs to start addressing these high development costs and to worry less about die shrinks of 5% to 10%. “EDA companies should help customers develop hardware/software systems,” he said. That’s a much bigger problem than the EDA companies are addressing today. (Note: Abdi’s perspectives closely parallel the Cadence System Realization initiative and the company’s recently introduced System Development Suite.)

Matar then took his turn speaking: “Integration is the name of the game.” Here, Matar was specifically referring to high-speed IP cores, GHz clock rates, dual- and quad-core microprocessor complexes, and low-power design. Matar then made a call for more collaboration between semiconductor foundries and EDA companies. “Lack of [design] innovation forces overdesign to overcome ecosystem deficiencies” he said.

Nakamoto then said “EDA has done some things right. For example, the amount of effort needed to supervise design rules has not gone up exponentially while rule complexity has.” Also, he said, EDA has dealt well with tapeout bulges. It’s handled peak loading well.

Abdi wasn’t so sanguine about IP. “You need five engineers to verify a 3rd-party IP block” he said. That’s in addition to what you need for system-level verification. Lanza agreed, saying “IP use is too difficult. You can’t make IP blocks from various vendors work together.” And that’s important, continued Abdi, because no more than 20% to 30% of an SoC’s design will consist of your own IP. The rest will be 3rd-party IP. Later in the panel discussion, Abdi continued this thread: “There are a lot of quality and verification issues with [today’s 3rd-party] IP.” Then Abdi asked “If it’s conforming to a standard, why doesn’t it work?” IP vendors can add more value by helping design teams integrate their IP into systems, he said.

Matar switched subjects. “Software and hardware need to be codesigned” he said. “Hardware is no longer the long pole in the tent.” Nakamoto fell into step with Matar: “We’re spending the most money on hardware/software codevelopment.”

Then Abdi made a bold prediction: “Five to ten years from now, the best design houses will be chipless. They will consist of 10 to 20 software and system engineers. The chip design will be entirely outsourced. “Moore’s Law allows you to trade off transistors for time to market” and in the future, these design houses will accept somewhat less efficient silicon usage in exchange for an advantageous time to market he predicted.

About sleibson2

EDA360 Evangelist and Marketing Director at Cadence Design Systems (blog at
This entry was posted in EDA360, Silicon Realization, SoC Realization, System Realization. Bookmark the permalink.

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