Yesterday’s blog entry discussed FinFETs as a way to build advanced-process transistors with reduced leakage and improved performance. (See “Are FinFETs inevitable at 20nm? “Yes, no, maybe” says Professor Chenming Hu (Part 1)“.) There’s another way to eliminate the unwanted silicon in the FET channel and that’s by making that part of the channel “go away.” If you make the channel as thin as 2nm, there simply won’t be a short-channel leakage path said Hu. Even if you can’t get the channel to be as thin as 2nm, you end up reducing leakage by an order of magnitude for every 1nm of channel thickness reduction. This ultra-thin channel approach achieves the same objective as the FinFET approach: it reduces the amount of silicon in the FET channel and, in particular, it eliminates any silicon far from the gate. That’s the silicon that permits leakage.
Experimental evidence back in the 1990s gathered under the 1996 DARPA contract indicated that the channel thickness needed to be about ¼ of the gate length to significantly cut short-channel leakage. Hu dubbed this sort of structure UTBSOI (Ultra Thin Body Silicon on Insulator). With the 4:1 ratio, a UTBSOI FET with a 20nm gate length needs a channel thickness of about 5nm. And indeed, in 2009, IBM started publishing experimental results with extremely thin SOI (ETSOI) transistors that have 25nm gate lengths and 6nm channel thicknesses. To achieve this manufacturing feat, you need SOI wafers delivered with very consistent silicon thin films. The film thickness must be within plus or minus 0.5nm across the wafer.
Soitec, a materials vendor that specializes in supplying SOI wafers, achieved that target two years ago by delivering SOI wafers with 15nm thin films that are consistent to within plus or minus 0.5nm across the wafer. The company’s Xtreme SOI wafers now offer silicon thin films that are as thin as 10nm with layer uniformity “guaranteed to within +/- 5Å at all points on all wafers.”
FinFETs and UTBSOI FETs offer many benefits over today’s planar MOSFETs:
- Better signal swing
- Less sensitivity to gate length and drain voltage
- No random dopant fluctuations
- No impurity scattering (especially important for designs that use sub-threshold transistor voltages)
- Less surface scattering
- Higher on current and lower leakage
- Lower Vdd and therefore less power consumption
- Smaller die area and therefore less die cost
However, said Hu, there are also important differences between FinFETs and UTBSOI. In UTBSOI’s favor, it’s relatively easy to add back biasing under the channel and beneath the insulating layer, if that’s desired. There’s no easy way to add back biasing to FinFETs without cutting the gate in two but you could do it.
The biggest difference, said Hu, is which entity is responsible to controlling the key FET parameters. For FinFETs, the key metric is the ratio of fin thickness to gate length. Both of these dimensions rely solely on the lithographic and etching processes and both of those are under the fab’s control. For UTBSOI, the key metric is the ratio of the channel thickness to the gate length and Soitec is largely responsible for controlling the film thickness in the wafers supplied to the fab. Consequently, said Hu, UTBSOI may be ready for production sooner but FinFETs have better long-term scalability.
Looking to the immediate future, Hu says here’s what will likely happen. Intel will use FinFETs in its 22nm manufacturing process and may well be able to continue using them “beyond 10nm.” Meanwhile, other semiconductor manufacturers and foundries may use UTBSOI for 22nm or 18nm processes to gain market share or protect existing market share.
“Competition will bring out the best in both” approaches, said Hu.