Xilinx 28nm low-power SoC design class, part 3: Optimizing the transistor mix

Xilinx wants you to have a quick course in 28nm low-power SoC design… for free. The company recently published a White Paper titled “Lowering Power at 28nm with Xilinx 7 Series FPGAs” but don’t let that title fool you. This White Paper is an authoritative guide to the many ways you can cut static and dynamic power in nearly any chip design that will be manufactured at advanced process nodes like 28nm or 20nm. This White Paper is so incredibly comprehensive that I simply cannot summarize it in one blog entry, so I have sliced it into six relevant pieces and am discussing the most significant topics over several blog entries, one each day this week. Be sure to come back each day for the next installment in the series.

Today’s discussion of the Xilinx White Paper focuses on the on-chip transistor mix. The more the merrier.

Having more transistor types to pick from complicates the design process but ensures a more optimized design. The Xilinx White Paper says that the company has increased the number of transistor types for the Series-7 FPGAs compared to the number used in the Virtex-6 parts. In addition to three threshold voltages (Vt)—high, medium, and low—the available transistors also come in several gate lengths and widths. Each of these transistors has unique performance and leakage characteristics and there’s a 15x to 20x difference in leakage across the range of transistor types.

Sorting out which of these many transistors to use could be an overly complicated problem so there is a transistor-selection algorithm used here. First, each block is designed with transistors that have the lowest leakage. These are slow transistors and they will cause negative slack in critical paths. So the next step is to swap out the slow, low-leakage transistors with progressively faster ones to meet the block’s timing requirements. This approach coupled with the use of the TSMC 28 HPL process technology (See yesterday’s EDA360 Insider blog entry) reduces static power dissipation by 65% compared to the company’s previous-generation FPGA.

Note: The first blog entry in this series on the Xilinx 28nm low-power SoC design White Paper was “3D Thursday: 28nm design and 2.5D packaging saves Xilinx a ton of power. You can too even if you’re not designing FPGAs!


About sleibson2

EDA360 Evangelist and Marketing Director at Cadence Design Systems (blog at https://eda360insider.wordpress.com/)
This entry was posted in EDA360, Low Power, Silicon Realization, SoC Realization, System Realization and tagged , , , . Bookmark the permalink.

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