Xilinx 28nm low-power SoC design class, part 4: Power gating RAMs

Xilinx wants you to have a quick course in 28nm low-power SoC design… for free. The company recently published a White Paper titled “Lowering Power at 28nm with Xilinx 7 Series FPGAs” but don’t let that title fool you. This White Paper is an authoritative guide to the many ways you can cut static and dynamic power in nearly any chip design that will be manufactured at advanced process nodes like 28nm or 20nm. This White Paper is so incredibly comprehensive that I simply cannot summarize it in one blog entry, so I have sliced it into six relevant pieces and am discussing the most significant topics over several blog entries, one each day this week. Be sure to come back each day for the next installment in the series.

Today’s discussion of the Xilinx White Paper focuses on power gating for memory.

Every advanced SoC uses clock gating to cut dynamic power but power gating is another matter. It’s especially important for FPGAs because it’s not clear at manufacturing time which blocks will be used and which will be unused in any given FPGA-based design. According to the Xilinx White Paper, the company’s earlier FPGAs have used power gating for a variety of on-chip blocks such as I/O transceivers, PLLs, DCMs (digital clock managers), and I/O pins. For the Series-7 generation, Xilinx added power gating to the on-chip block RAM as well.

With some development history behind it, Xilinx analyzed leakage in many customer designs and discovered that nearly 30% of the total leakage in these designs could be attributed to the on-chip block RAMs.The Xilinx design software for the Series-7 devices now examines block-RAM usage and switches off the power to unused block RAMs. It seems like an obvious thing to do, but it’s only obvious if you look.

And that’s the lesson from this particular section of the Xilinx White Paper. Advanced SoC designs are less and less likely to be operating all on-chip RAM blocks simultaneously and all the time. A lot of power can be saved by switching off the power to these blocks when they’re not used. This lesson is even more important for your garden variety advanced SoC because most of those SoC designs employ a lot of RAM. In fact, most of today’s SoC designs contain many RAM blocks and are more than 50% memory as measured by silicon area, so cutting power to unused memory blocks can produce significant power savings.

Easier said than done. It’s one thing for Xilinx to switch off the power to a block RAM that’s never used in a design. The design tools can easily detect that situation at build time. If you want to design a system that actively switches RAMs on and off during operation to save power, that goal has some significant implications at all design levels: System Realization, SoC Realization, and Silicon Realization. This is a harder path to take, yet it’s clearly the path we’re on.

For additional information, see these two Cadence White Papers: “Low-Power Design for Highest Quality of Silicon” and “Creating Low-Power Digital Integrated Circuits – The Implementation Phase.”

Note: The first blog entry in this series on the Xilinx 28nm low-power SoC design White Paper was “3D Thursday: 28nm design and 2.5D packaging saves Xilinx a ton of power. You can too even if you’re not designing FPGAs!

About sleibson2

EDA360 Evangelist and Marketing Director at Cadence Design Systems (blog at https://eda360insider.wordpress.com/)
This entry was posted in EDA360, Low Power, Silicon Realization, SoC Realization, System Realization and tagged , , . Bookmark the permalink.

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