Xilinx wants you to have a quick course in 28nm low-power SoC design… for free. The company recently published a White Paper titled “Lowering Power at 28nm with Xilinx 7 Series FPGAs” but don’t let that title fool you. This White Paper is an authoritative guide to the many ways you can cut static and dynamic power in nearly any chip design that will be manufactured at advanced process nodes like 28nm or 20nm. This White Paper is so incredibly comprehensive that I simply cannot summarize it in one blog entry, so I have sliced it into six relevant pieces and am discussing the most significant topics over several blog entries, one each day this week. Be sure to come back each day for the next installment in the series.
Today’s discussion of the Xilinx White Paper focuses on intelligent clock gating. It’s all about automation, baby.
A fast way to cut dynamic power consumption is to stop the clock. Turn it off. Cease the switching. It can take time to figure out where to gate clocks without altering a block’s function. According to the Xilinx White Paper, fine-grained clock gating can cut dynamic power consumption by 30%. Consequently, Xilinx has added automatic, intelligent clock gating to its ISE Design Suite 12 design tools to add clock gating without altering the design’s function. Most ASIC/SoC synthesis tools, such as the Cadence RTL Compiler, incorporated automatic clock gating a while ago. (See these two Cadence White Papers for more information: “Low-Power Design for Highest Quality of Silicon” and “Creating Low-Power Digital Integrated Circuits – The Implementation Phase.”)
Frankly, automation is really the only way such clock gating can be added going forward. SoC designs are simply too big to do this by hand any more. Automated clock-gating tools make life much easier.
Note: The first blog entry in this series on the Xilinx 28nm low-power SoC design White Paper was “3D Thursday: 28nm design and 2.5D packaging saves Xilinx a ton of power. You can too even if you’re not designing FPGAs!”