Xilinx 28nm low-power SoC design class, part 6: Vccaux, the “other” power supply

Xilinx wants you to have a quick course in 28nm low-power SoC design… for free. The company recently published a White Paper titled “Lowering Power at 28nm with Xilinx 7 Series FPGAs” but don’t let that title fool you. This White Paper is an authoritative guide to the many ways you can cut static and dynamic power in nearly any chip design that will be manufactured at advanced process nodes like 28nm or 20nm. This White Paper is so incredibly comprehensive that I simply cannot summarize it in one blog entry, so I have sliced it into six relevant pieces and am discussing the most significant topics over several blog entries, one each day this week. Be sure to come back each day for the next installment in the series.

Today’s discussion of the Xilinx White Paper focuses on Vccaux, the “other” power supply used to power certain key components in the FPGA.

Most FPGAs use an auxiliary power supply rail to power certain architectural-level blocks such as PLLs and I/O buffers. For the company’s Series-7 FPGAs, Xilinx reduced the Vccaux supply voltage spec from 2.5V to 1.8V, which reduced static power consumption for those blocks by approximately 30%. Many SoC designs could use the same approach but the Silicon Realization teams will be trading off reduced power consumption for added design complexity to do so. As the Xilinx White Paper says, it takes an architectural approach to make such decisions. Like all of the design decisions discussed in this 6-part blog series, these decisions touch the design at the System Realization, SoC Realization, and Silicon Realization levels.

The purpose of these six EDA360 Insider blog entries is not to say “Design the way Xilinx does.” After all, we’re not all designing FPGAs. However, Xilinx has been generous in sharing all of this information with the design community and the FPGA companies are certainly towards the head of the pack when it comes to 28nm IC design. Further, all SoCs have similar sorts of architectural-level blocks, so it’s worthwhile to pay just a bit of attention to this White Paper even if you don’t use FPGAs.

For more information on designing SoCs with multiple power domains, see “Power-Aware Verification Spans IC Design Cycle: A Plan-to-Closure Approach Helps Ensure Silicon Success.”

About sleibson2

EDA360 Evangelist and Marketing Director at Cadence Design Systems (blog at https://eda360insider.wordpress.com/)
This entry was posted in EDA360, Low Power, Silicon Realization, SoC Realization, System Realization and tagged , , , . Bookmark the permalink.

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