Over the past week, I’ve published a 6-part series of blog posts based on the Xilinx White Paper describing how the company developed the low-power aspects of its Series-7 FPGA families. The lessons apply to any team developing ASICs and SoCs with an eye towards minimizing power consumption. Here are the six parts:
- 3D Thursday: 28nm design and 2.5D packaging saves Xilinx a ton of power. You can too even if you’re not designing FPGAs!
- Xilinx 28nm low-power SoC design class, part 2: Process Technology
- Xilinx 28nm low-power SoC design class, part 3: Optimizing the transistor mix
- Xilinx 28nm low-power SoC design class, part 4: Power gating RAMs
- Xilinx 28nm low-power SoC design class, part 5: Intelligent clock gating
- Xilinx 28nm low-power SoC design class, part 6: Vccaux, the “other” power supply
EDA360 Insider 