6-Part series of blog posts on 28nm low-power design

Over the past week, I’ve published a 6-part series of blog posts based on the Xilinx White Paper describing how the company developed the low-power aspects of its Series-7 FPGA families. The lessons apply to any team developing ASICs and SoCs with an eye towards minimizing power consumption. Here are the six parts:


About sleibson2

EDA360 Evangelist and Marketing Director at Cadence Design Systems (blog at https://eda360insider.wordpress.com/)
This entry was posted in EDA360, Low Power, Silicon Realization, SoC Realization and tagged , , , , . Bookmark the permalink.

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