Imec and several of its 3D integration partners (Globalfoundries, Intel, Micron, Panasonic, Samsung, TSMC, Fujitsu, Sony, Amkor, and Qualcomm) have fabricated a 3-chip 3D IC stack demonstration prototype with the intent of proving several assembly methods plus electrical characteristics and thermal simulation techniques currently under development. The demonstration 3D stack includes a custom-designed CMOS chip and a commercial DRAM chip. Through-silicon vias (TSVs) and copper-tin micro-bumps attach the chips in the stack, which was assembled with thermo-compression bonding. The prototype stack design incorporates on-chip heaters to test the impact of thermal hotspots on stack heating and on DRAM refresh times. Additional test structures monitor thermo-mechanical stress in the 3D stack, ESD (electro-static discharge) hazards, and the electrical characteristics of the TSVs and micro-bumps.
Here’s a photo of the chip stack:
The base chip is approximately 750µm thick. The two top components in the chip stack are each 25µm thick.
Here’s a close-up image of the stack edge:
This 3D integrated DRAM-on-logic demonstrator has already produced valuable data. For example, results indicate that a minimum die thickness of 50µm is required to deal with local hot spots on the logic die. Hot-spot temperatures run higher and are more confined locally as die thickness shrinks. Hot spots on the logic die also raise the local temperatures in the memory die, which can reduce DRAM retention time due to increased leakage from thermal effects. Imec’s 3D stacked demonstrator proved that the DRAM die will also act as an effective heat spreader for the logic die, which reduces the hot spot’s maximum temperature. The results of the various experiments allowed Imec to calibrate its 3D thermal models as implemented in associated 3D EDA tools.