Open-Silicon’s Naveed Sherwani speaks about the verification crisis in SoC design with unusual clarity

Last month at DAC, Richard Goering interviewed Open-Silicon CEO Naveed Sherwani for ChipEstimate.tv. The main topic was Open-Silicon’s new “on time or on us” chip delivery program but the last few minutes of the 11-minute video interview cover the very important topic of the looming verification problem that overshadows SoC design. As long as we verify every chip design as though it was developed from scratch, the verification task grows exponentially along with the transistor count. Only by breaking the verification task hierarchically and by ceasing to re-verify portions that are already silicon –proven can be escape the verification trap. It’s really an essential part of the IP-reuse concept.

Well worth watching for these last few minutes. Sherwani hits this nail precisely on the head.

http://www.cadence.com/Community/blogs/ii/archive/2011/07/17/video-open-silicon-ceo-warns-of-exponential-verification-nightmare.aspx?CMP=home

About sleibson2

EDA360 Evangelist and Marketing Director at Cadence Design Systems (blog at https://eda360insider.wordpress.com/)
This entry was posted in EDA360, Silicon Realization, SoC Realization, Verification and tagged . Bookmark the permalink.

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