3D Thursday: EETimes backs away from an apples and oranges comparison. Makes fruit salad

Earlier in July, Dylan McGrath at EETimes published an article about a report that pitted TSMC and Intel in a race to 3D. Unfortunately, there’s not really a race. TSMC’s efforts are towards 3D chip assembly. That’s the kind of 3D that gets the most attention in 3D circles. Intel’s version of 3D, which Intel calls “Tri-Gate” transistors and everyone else calls FinFETs, is a program to build 3D structures on a monolithic chip. Both are 3D technologies but with very different objectives. The TSMC-style 3D approach permits the ready mixing of various process technologies and nodes. This type of technology eases the interconnection of logic, memory, analog, and RF die using micro-bumps and compression bonding. Intel’s Tri-Gate FETs, which Intel plans to introduce with its 22nm process technology, creates faster transistors that leak less—a very different objective. So if there’s a race, the two competitors are racing on different race tracks.

A week later, McGrath set the record straight and called the comparison a “false equivalency.” It’s a gutsy thing for an editor to do.

More on Intel’s Tri-Gate transistors:

3D Thursday: Intel and FinFETs (Tri-Gate transistors)—a different kind of 3D

3D Thursday: Daniel Nenni writes about Intel FinFETs


About sleibson2

EDA360 Evangelist and Marketing Director at Cadence Design Systems (blog at https://eda360insider.wordpress.com/)
This entry was posted in 3D, EDA360, Silicon Realization, SoC Realization, System Realization and tagged , . Bookmark the permalink.

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