Friday Video: What’s Next For Memory Designs In 2012? – from Agilent

Agilent has created a 6-part video series titled “What’s Next For Memory Designs In 2012?” that’s well worth a look. There’s about 30 minutes of video total, chopped into 2-8 minute pieces that you’ll want to watch if you have any connection to memory use in System Realization. (Note: the YouTube versions of the video are much clearer and you can see them here: http://www.youtube.com/watch?v=g_8NPc5zf2U) Like everything else, memory has been getting faster and faster to accommodate the exponential data needs of media-centric devices that are now the norm in our world rather than the exception.

The videos are hosted by Perry Keller, Digital Applications and Standards Lead and Memory Program Manager for Agilent. It’s clear that Keller knows a lot about the problems associated with high-performance memory use and he discusses several important topics in these videos including the looming memory wall where memory bandwidth is just not going to get any better without something disruptive shaking up the technology. Some of the disruptive developments Keller discusses in these videos include 3D assembly and Wide I/O, topics frequently covered in the EDA360 Insider. For example, see:

The DDR4 SDRAM spec and SoC design. What do we know now?

Herb Reiter on the 3D landscape as he sees it today

Wide I/O. Don’t leave your SoC without it 

I wish I could bring these videos to you directly, but Agilent has used a proprietary video player. Also, I wish the videos were larger because the PowerPoint slides are right on the edge of being unreadable at the published video resolution. Publishing these videos on YouTube in HD would have helped a lot. Nevertheless, the material in these videos is valuable enough to brave the inconveniences.

Watch the videos here.

(Note: Watch the YouTube versions of the video. They are much clearer and you can see them here: http://www.youtube.com/watch?v=g_8NPc5zf2U)

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